.TITLE DZD ; * * * ID-2000/5000 DEVICE HANDLER FOR RT-11 V03 OR V04 (DMA) * * * ; DE ANZA SYSTEMS, INCORPORATED ; ALL NEW CODE: 13 APRIL 77 ; MODIFICATIONS INCORPORATING DMA: 21 JULY 78 ; REVISIONS TO: 19 OCTOBER 78 ; RT-11V03 MODIFICATIONS: 8 JANUARY 79 ; CONDITIONALS FOR ID-5000, WORD COUNT = 0 CORRECTIONS: 29 JUNE 81 ; PROGRAMMER: KEN DINWIDDIE ; IMPLEMENTS BI-DIRECTIONAL 16-BIT WORD TRANSFERS BETWEEN ; DIGITAL EQUIPMENT CORPORATION 11 SERIES COMPUTERS ; OPERATING WITH THE RT-11 OPERATING SYSTEM AND ; DE ANZA SYSTEMS, INCORPORATED 2000 SERIES IMAGE DISPLAY SYSTEMS. ; TRANSFERS OF TWO DIFFERENT TYPES ARE PROVIDED: ; (1) READ/WRITE TO ANNOTATION OR INTENSITY TRANSFORMATION ; TABLE - STARTING BLOCK NUMBER SPECIFIES X-ADDRESS > 1777. ; (2) READ/WRITE TO IMAGE REFRESH MEMORY - STARTING BLOCK ; NUMBER SPECIFIES X-ADDRESS 0-1777; FIRST THREE WORDS OF ; BUFFER CONTAIN Y-REGISTER, BIT-PLANE MASK REGISTER AND ; CONTROL/STATUS REGISTER RESPECTIVELY. A MAXIMUM OF ; 256 (ID-2000) OR 512 (ID-5000) WORDS MAY BE TRANSFERRED ; PER TYPE 2 CALL. ; NOTE: JOYSTICK INTERRUPTS ARE FLAGGED AS ERRORS. .PAGE .SBTTL HANDLER DEFINITIONS .MCALL ..V2..,.REGDEF .MCALL .DRBEG,.DRAST,.DRFIN,.DREND,.QELDF ..V2.. ; REGISTER DEFINITION .REGDEF ; QUEUE ELEMENT DEFINITIONS .QELDF ; RT-11 MONITOR DEFINED CONSTANTS HDERR =1 ; HARD ERROR BIT ; ID-2000 COMMUNICATION CONSTANTS GO =101 ; TRANSFER AND INTERRUPT ENABLE READBK =117 ; READBACK AND INTERRUPT ENABLE DZVEC =234 ; INTERRUPT VECTOR ADDRESS ; ID-2000 CONTROL REGISTERS (DMA SYSTEM) XREG =166020 ; X-REGISTER ADDRESS YREG =166022 ; Y-REGISTER ADDRESS BPMR =166024 ; BIT-PLANE MASK REGISTER ADDRESS CSR =166026 ; CONTROL/STATUS REGISTER ADDRESS DREG =166030 ; DATA REGISTER ADDRESS .PAGE ; DMA REGISTERS DAWC = 166040 ; WORD COUNT DABA = 166042 ; BUS ADDRESS DACS = 166044 ; CONTROL/STATUS ; DMA OPERATION CODES DMARD = 504 ; READ WITH INTERRUPT AND CYCLE DMAWR = 502 ; WRITE WITH INTERRUPT AND CYCLE ; INTERRUPT FLAGS DRDY = 20000 ; DISPLAY SYSTEM WCZ = 10000 ; WORD COUNT ZERO (DMA) JYKN = 4000 ; JOYSTICK/KNOB (CURRENTLY ERRONEOUS) ; DEFAULT SYSTEM BUILD PARAMETERS .IIF NDF MMG$T,MMG$T = 0 .IIF NDF ERL$G,ERL$G = 0 .IIF NDF TIM$IT,TIM$IT = 0 ; DEVICE STATUS INFORMATION DZDSIZ = 20000 ; DEVICE "SIZE" IN 256 WORD "BLOCKS" DZSTS = 100024 ; BLOCK STRUCTURED, #24 .PAGE .SBTTL ID-2000 DEVICE HANDLER .DRBEG DZ,DZVEC,DZDSIZ,DZSTS MOV DZCQE,R0 ; PICK UP POINTER MOV (R0),XADDR ; PICK UP X-ADDRESS MOV 4(R0),BUFF ; PICK UP BUFFER POINTER MOV 6(R0),WCNT ; PICK UP WORD COUNT MOV XADDR,@#XREG ; X-ADDRESS TO X-REGISTER CMP XADDR,#2000 BMI IMAGE ; IMAGE REFRESH TRANSFER IF < 2000 MOV #2,MFLAG ; SET FLAG TO WRITE TST WCNT ; WORD COUNT POSITIVE ? BPL DZRAM0 ; YES, SHOW READ NEG WCNT ; NO, NEGATE WORD COUNT BR DZRAM1 ; AND PROCEED DZRAM0: INC MFLAG ; SHOW READ OPERATION REQUEST DZRAM1: MOV MFLAG,R4 SUB #2,R4 ; OPERATION TYPE ? BEQ WRITE ; IF WRITE READ: MOV #DMARD,DMAMOD ; PREPARE FOR READ OPERATION BR TSTITT ; GO CHECK ON ITT TRANSFER WRITE: MOV #DMAWR,DMAMOD ; PREPARE FOR WRITE OPERATION TSTITT: JSR PC,ITTXF ; GO TEST FOR ITT TRANSFERS DMAXFR: MOV WCNT,@#DAWC ; SET WORD COUNT MOV DMAMOD,@#DACS ; SET OPERATION CODE, CYCLE, INTERRUPT ENABLE MOV BUFF,@#DABA ; SET BUFFER STARTING ADDRESS BIS #1,@#DACS ; INITIATE DMA TRANSFER RTS PC ; AND GO AWAY TO AWAIT INTERRUPT .PAGE IMAGE: MOV BUFF,R5 ; PICK UP BUFFER POINTER MOV (R5)+,@#YREG ; Y-REGISTER TO DISPLAY MOV (R5)+,@#BPMR ; BIT-PLANE MASK TO DISPLAY MOV (R5)+,R4 ; PICK UP CONTROL/STATUS TST WCNT ; EXAMINE WORD COUNT BNE IMAGE1 ; CONTINUE IF NON-ZERO MOV R4,@#CSR ; SET DESIRED BITS IN CSR IF WORD COUNT = 0 BR DZHOME ; AND RETURN TO MONITOR IMAGE1: MOV R5,BUFF ; RESTORE UPDATED BUFFER POINTER BIS #GO,R4 ; AND NEW CSR WITH GO AND INTERRUPT MOV R4,CSRSAV ; SAVE FOR FUTURE REFERENCE CLR MFLAG ; SET MODE FOR IMAGE WRITE TST WCNT ; WORD COUNT POSITIVE ? BPL DZIM0 ; YES, SET FOR IMAGE READ NEG WCNT ; NO, NEGATE WORD COUNT BR DZIM1 ; AND PROCEED DZIM0: INC MFLAG ; FLAG FOR IMAGE READ DZIM1: TST MFLAG ; WRITE MODE ? BEQ WRITE ; YES, START WRITING OPERATION MOV #DMARD,DMAMOD ; PREPARE FOR READ OPERATION MOV #READBK,R4 ; PICK UP READBACK WITH INTERRUPT CODE BIS CSRSAV,R4 ; INCLUDE CONTROL BITS SUPPLIED MOV R4,@#CSR ; INITIATE READBACK OPERATION BIS #100,@#DACS ; ENABLE DMA INTERRUPT RTS PC ; AND GO AWAY TO AWAIT INTERRUPT .PAGE .SBTTL INTERRUPT PROCESSING ROUTINE .DRAST DZ,6,DZHOME MOV @#DACS,R5 ; PICK UP DMA CSR CONTENTS CLR @#DACS ; CLEAR DMA CSR FLAGS BIT #DRDY,R5 ; DISPLAY READY ? BEQ DZINT2 ; NO, GO CHECK WORD COUNT ZERO BIT #1,MFLAG ; WRITE OPERATION ? BNE DZINT3 ; NO, GO CHECK FOR IMAGE READ BIT #2,MFLAG ; YES, IS IT AN IMAGE WRITE ? BNE DZINT4 ; NO, GO START DMA TRANSFER BR DZHOME ; YES, RETURN TO MONITOR ; WORD COUNT ZERO INTERRUPT PROCESSING: DZINT2: BIT #1,MFLAG ; WRITE OPERATION ? BNE DZHOME ; NO, RETURN TO MONITOR BIT #2,MFLAG ; YES, IS IT AN IMAGE WRITE ? BNE DZHOME ; NO, RETURN TO MONITOR MOV CSRSAV,@#CSR ; YES, ENABLE BUFFER TO IMAGE TRANSFER BIS #100,@#DACS ; ENABLE DMA INTERRUPT RTS PC ; AND GO AWAY TO AWAIT INTERRUPT DZINT3: BIT #2,MFLAG ; IMAGE READ OPERATION ? BNE DZINT4 ; NO, SKIP BIT 9 RESET .IF NDF ID5000 BIC #1000,XADDR ; RESET BIT 9 FOR BUFFER/CPU TRANSFER .ENDC ; BUFFER TO CPU TRANSFER AFTER IMAGE REFRESH TO BUFFER, ; OR ITT TRANSFER AFTER AWAITING VERTICAL INTERVAL: DZINT4: MOV XADDR,@#XREG ; INITIALIZE DISPLAY X BR DMAXFR ; GO INITIATE DMA TRANSFER ERROR: MOV DZCQE,R5 ; PICK UP CURRENT Q ENTRY POINTER BIS #HDERR,@-(R5) ; SOMETHING IS VERY WRONG DZHOME: .DRFIN DZ ; EXIT TO MONITOR QUEUE COMPLETION ; TEMPORARY STORAGE LOCATIONS BUFF: .BLKW 1 ; BUFFER STARTING ADDRESS CSRSAV: .BLKW 1 ; COMPLETE CONTROL/STATUS REGISTER DMAMOD: .BLKW 1 ; DMA OPERATION CODE MFLAG: .BLKW 1 ; TRANSFER MODE FLAG WCNT: .BLKW 1 ; TRANSFER BLOCK LENGTH XADDR: .BLKW 1 ; DISPLAY SYSTEM INITIAL X-ADDRESS .PAGE .SBTTL SUBROUTINE FOR MINIMIZING ITT TRANSFER VISIBILITY ITTXF: BIT #10000,XADDR ; ITT TRANSFER ? BNE ITTXF1 ; Yes, go perform dummy read RTS PC ITTXF1: TST (SP)+ ; PUSH STACK POINTER UP ONE NOTCH CLR @#YREG ; POINT TO LINE ZERO IN DISPLAY MOV #READBK,R5 ; PICK UP READBACK WITH INTERRUPT CODE BIS CSRSAV,R5 ; INCLUDE PREVIOUS CONTROL BITS BIC #40,R5 ; CLEAR ZERO BIT IF SET (DO NOT SET "V" BITS) MOV R5,@#CSR ; ENABLE READBACK WITH INTERRUPT BIS #100,@#DACS ; ENABLE DMA INTERRUPT ITTXF3: RTS PC ; GO AWAY TO AWAIT INTERRUPT .DREND DZ .END