IMD 1.16: 5/06/2007 18:32:15 64620-12003 Rev. 2350A State Analyzer 2 of 2  D #?DGC} ]24!!!!!!!!!!!!!!!!!!!!N64620-12003 STATE SRS ABSOLUTE S-64620-12003-1 RVA 0202 DESIGNER BRYCE GOODWIN 2350 HEWLETT PACKARD                            ! " !#"$  #%$&  %'&(  ')(*  )+*,  +-,.  -/.0  /102  1324  3546  5768 798: 9;:< ;=<> =?>@ ?A@B ACBB database HP GG ]4 ]4pv_am1100HP ZVVgpv_prepF0HP Z[\D@pv_prep80HP ZWZ @ssmmtmp3 HP(hp)[\ ]4 ]4pv_64620 HP ZHU4  ]Cg}AD PV_STATE 16 Dec 1983 21  pv_64620 :HP :0001H  pv_am1100:HP :0001H  pv_prep80:HP :0001H  pv_prepF0:HP :0001H  `  /*qk\C$87?llllllPass Fail 76543210 98765432109876543210 (1 = Error)q0q,uB2, 1 t52u<3o0ţĀuError: System softwardatabase was not upded (file tapebase:HPot found) FަWȐB3D4DNDDD4BBBt B5EE9tD6B5Searching for AIMB stimulus boardsAwaiting command 7D8D8D 7D A72&B (L A0(CBqh|j0830B3qxuqq}lKoKo3 L5'3 /\'L D7Al Dh-ɰ0oo 3G2 A7fL3 (A dD[oD2 ?VK3Sl A9 C5" 0D0quqq}lo]ol=lA74 5 A7.58 (LtB (LAڑ9l& D7Ao D(L (LްLDG (L`Ұpv_prep00HP  %K3%H3DKK& C0 L A30qxuqq}loKK[oDoӳB3B3Du CDf"l:%DKKLoc7AoD D A0%&}0$qqqit~0830qxuqq}loKo~08qx(Ll:&l(8HoA2& (L:&o.i'3DlD9&=t :%\"&3҈G&"R*&0o1{5A3z  A64$# l l $AA9lB D D!pv_am0000HPA6L0 00lKlJlIl( ,F A5AB#’B7o66oA4 4l@22 -8|oIntermodule Bus might not be reset, slot 0 (reset at power up)F.D@8@CB`4 @5LlA$RlA,R<| B5DW?)*-BǞotgt7soDl$OkD<4A7mD"C7ddCDD\0MOYXMl " uXo7NA7SB7IoDA7LC'A'J CAA C<B@9g777B74 /,IH/3G' ]u>ECl WlGCD/lk 0 C0DXllbqxuHo@Slot "“)@Preproc "“*/@PASSED@FAILEDD 10 MHz Verification PASSEDSSlot nn, Test nnin process A6AAD w|4A;(AeR@[ˊAyi(8XoBeCefDeEef@10 MHz State Test: A@ Configuration pHQDiH@includedDj4x3Q3 373M33D8[lAV 3[lF383L3D#[lAa4L 3[lG383B3D Ad j3[ot 7tAll4 L<3Al$ }#Ѐ/;3B 7tAA;#3 |:lB&A;"3A j3[lKKoQDiH@excludedFHDjpPi ` `  `@preproc ` `Ih2I╄` ` `Dh"`Dj` ` H@am @:HP IpP`@preproc ` `H@prep @:HP ? Slot ID Description Part Number Boards for IMB testingFile not found: pv_10 MHz boards AY3Q3 373΃tl!'3BAA; M3"3 #р'P3Am j3[lKKo3Q3 373΃tl M0 H3 C3 C3A j3[lKKo@All Boards Test Summary pPPDP` ` @preproc `  `"`IpP8#`#`աHkHn Slot ID #Tests Description Tested Failed Last DRB4GlDLB/DHB,DDB)D@BA6D9`!DG"|@A6D(#oA6D!˼GG̼oAABBDEFGHIKLMNJOpPRhhh`oL0 *lL0 :PQA6GF0O3η|~XoD-UUUUA6GD0OJͷXoXoGBA6GR8BDXoaB`PQ﷬GHA67GއO0BGOXooA6GlA6G7RDXoGB~A6G(A lA6G3ol|~iA67GO0BR0R0GXouOXoA67GO0Bb0J0GXouOXoGL@BPMlN4`A6G>?| 0`P2P7PQ0D%`P2P7F C/G0B0DXDݷOuJ IXoC AP7_o H&BP0P} +L(:+F`4FFMb+2+G`IPQA7A6FF7AB7D OJlOoD0IOO_oD%B}C`O_o$#< C<FFBR7F`D0P_o77J7=???????FzBѶjn+FuBѶeXoFoB`A6Fh CBVt '(A8BqiXo7`7P`WR7B~`_ou`*'ub)2)3Kˋ;7 C0 C0PQ0PG`0PQ`0P`l C0 C07C`HCPQPQGu`7PEu`7A.DG@Interactive Read Error Dj @Trace memory @Overview memory, flags pN' D '4' CTVdd d '8B(C'' C3At0@ Reference = I`Threshold circuit calibration+ 0 V Zero level - 4.267 V Negative limit + 4.233 V Positive limit - 3.333 V +10V threshold + 3.333 V -10V threshold + 433 mV ECL (-1.3V) - 467 mV TTL (+1.4V) `O` j72**Bl*" 76'$J**7 C2( C2'/߈?ӀP7рG7 'B2(Z'A67GB2)2+KB0GL'DMB0HLK2*:l" NB* A5:OBϕlϓP ( )(u}HlHAA6GA {'7}7yC7x7vAG}OqO_kl_ioAGqA7aoA67GjS'^' A7PAH'S'4AA6GODA7:B7tOsGHAG=k,+G8oA67`G3DЇB'3ˀ3' 'Q Al*A6C7JG'Q7B7=O Bm89 %lP?%3 A5>=P52%05 )R5E540%253-KJ-l +%,5.-5*5l'P5$H55 A5` Bl"l  C5%a5 C54l  C5H%T4P4Fll4ooo %Fl]Bll S4l745 C02 A0=qpqh|~ A4$ %( A4E4P4$ A4$ A4 A5  A4` Bl l  C44 C44l  C4H4P4ll4oLo TA $l$ $} A4l $4~$4sl $H4t$P4h A4kb4^oB4 C4 HlP $Rl NS0$KI C4G$ A4I\$? $ A4YXE4WS$U A4TP$Q A4QKKl L C4J4-H C4F4$l A C4?H4!;P4Bllllo4  $mlnoo|nB99AMM4 LL\oBF4 huBB4e C<4 @L \olg,DENOMINATOR IS 0ps@?aiBAA@@@@AB@@@ ABEFGIJK6k p#$)0*%$r',(qs-jMNOPQRS\.]0]^ LAAADAAAAa+  t. 35 .> ?"0$&&0"l "mn "!"o <H7C98; =(6*:,D //,,14b&b0bLcT.Ud.VefWgXYuh[_i`2hZißd:?GB5{{{L$O{|{u`{r{{{u`{{{{{{{{{{{{u`{{|{{{r{{{{{{{{{{{{{{{{{{{{{{{{{{[{{{{{{({{{{{{{{{{{{{{{{{{{{{{{{{{d:?{L$O5{{{{O{{{{{{{{{{ ---ETC--- all_boardsappendcomment configuration default display end exclude include listmessage preprocessorprinter repeatrun test_IMB_with stoptest till_fail all_board config. preprocU test_IMBh stop ʟޟ07Command is complete to cursor positionSlot number containing included board Slot numbeL Kr containing excluded board Slot number containing AIMB stimulus boardTest to run on board in selected slot Listing fileCharacters delimited by ^ ' or "H           = Vuu -ˀA@33-CA >BU3Al #4@Bl DlFl"Gl'Il-Kl)Bt= .A<,<,F 2Ae C0qX! @yhuyqyiXoGB FDClA5ECA2B G`7unrecognize>probe Bno probe connected MUNIBUS interface WHPIB interface `a BPC interfaceigeneral probes rHCBPC HPjuser interface 00hCUSER00HPuser interface 01hCUSER01HPuser interface 02hCUSER02HPuser interface 03hCUSER03HPuser inqAV53i᡾Syntax errorD333AAWA@;r4ƂX3wY33x33A34@Z A x;W7u=7tBl@lAbx]B77^b4)52,HLFcdx]YulS4R4Q44./0 ueflgY7w;;xB7;7=2Selected test number unavailableDSelected board or preprocessor not in included list ` Board not in excluded listoNo control board in included list No preprocessor attached to control board Board not in included list Board not in IMB list File not found for IMB board Disc number 0 to 7 only Comment maximum 80 characters xYlh 8Fh0u B hMLhD6dV5: " 0BF:h:DLih&jxYl Lt: RG68h D38.tXG6i6xYlh 8 h0u BFhhl6QoA:D 6xYl Lup(G0CquuqloovƥvƥI=pP (0 emulation bus CTMS320_EHPNSC800 interface NSC800 emulation bus hCNSC800HPCNSC800_EHP16008 interface16008:"lation bushC16008 HPC16008_E HP16032 interface16032 emulation bushC16032 HPC16032_E HP32032 interface32032 emulation bushC32032 HPC32032_E HP32132 interface32132 emulation bushC32132 HPC32132_E HP9450 interface 9450 emulation bus HC9450HPhC9450W_ly ~;ܯΰ2Hk֦,Ḙ.T=VAfȨEl{_ '6?IJM^PEEEEEEEEEeEEState Control and Clock64621A STATE-CT Ѧߦ1 Mainframe interface and stimulus Control IC - shift registerClock IC - shift register Sequencer State count Trace memory Other counter testsIntermodule BusStrobe generator calibration #Preproc interface data bus stimulusRear panel PORT stimulus A6OP۷`@`?hC awxyzw{|BC}B~GI€w:3K:l" OB܂: A5˲:{FGIJUUD‚w{ƒID/„ƒD,C…DD~|}}D"~}}|D~}AB~Ct#tq0"|@ APl oB‡̷XoqDPF‚wDl]A;W UDU UDA O00;K|3 #3R33l[lR3Hu A3t0lBDPN MlA …[l[oR3HoB`AP0 B3L3GlE†D[oD L3GlE†[o`P3A﨎@ Register data =@All 0's 7@All 1's 1@Patterns@ Shift control @)NOTE: This tests only the shift register.  HkHnP` ̠Hn`H` Hn@ Not- HHkp@ Load ModeEPE‚D xˆ{#t@ƒtD†wA;w@ BDA CDB H00;KR3 #3J33l[lJ3Hu A3t0lBÇEPE0IPE …[l[oJ3Hoة UWUUAL0@Register input bits `Di@10Dj@All 0's H@All 1's @Patterns@External Clocks HkHn@ , not blocked ̐IJKLMNpQPT@@/@?@` $@/@@/@ @ @K‚wx*DD>DE m+}B‡E~B†B33Ew IB…EK[o‰AB3R3Їu񃷖XoE] (CG(FIC…K[oŠ}A~qEKNICw~qDDDQDBBDŠ~p3AEPHDEA[o~q3AEEFD{BEAHD{E2[o~r3BE6FDlE'[o~s3BE+HDeE[owAE#‹y‡ˆz@EtD[„DuDVŒ}A}BDRBDlEG…[[oR3DDDl',F…[[oE[oJ3'3BD/-0qpBBDlG…[[o'A@t%0DD}Dl DtlDuDEa3R3wu~ˆ„DCDz~DD w*{D0DlI0D`P`H@3w~‡vXo€{‡zDylI†DzuI†Ko<33w~ˆzLD`uD$DcuD!w F3~KˆzLDO3K˃uoKlD[˃Kl DBu6JClGD:u9 y$A;mB@=D?DB99`PGP˶,*G`PQB B#%`P PGAuE@uo"}<θ CoAj $ ̾ `@Reset Hn`P ̐ `@ No carry@ Inc @ Load @ Early carry p4 ̐\ ̐ ̀HnHk HnHkP Di@54321_98HqDjQ@State Register Count_@Load@Occur Counter BiONts True c@False K@RAM H1@MemoryH1,@ , Trace Point @SequenceH1@ing Y@ Functions h#@(HSTR,LSTE,LSSE,LSME)  Address 7VM‚D DD=DYDe+BŽAhwDDDqDp`PQC…`DDG3ŒD„ŒD|„[oDYP0AE…B @A?FGDG08AqyDꅈBDZzMl0ﬔﬗDUHGHGDGz:DHoDFL3˃uAD9zDK0L0QDKHADKoD*{„|BC7qGPQ7nn7l3̓ˈIS3΃`DS…X $(~-~,1l0l/+V + C a c b /?/jHDiHvDjR@ Reset to 0*H@ Count enable@ 10/10 count@ 20 bit count@ Output test S@0's P@1's !!3)%@: ̠@ never enabled @CE input stuck high @always enabledh<HnHkP!!KKK[[3IpPSTC aW`H` @/O‚xD D@DiDDD+BDEC†ED†EE†DD IC…D ID…DE…„K[oDC…DD…DIE…~zDDDIC…DD…DEIEDD$zAD ‡{3D„[oB3D3|B IP IF…K[o‡ztw}A~{x3w€zw€„[oG3iB3;DzDK[o|C I3 … I3 (C{zI3HAo{„B3C3w€zK 3̃3l w€zoL3D;A3!0qploAl3B3;GcuK…K[owˆzD w~ˆzD„D"wlDvNw~B333B؆`P`PPEAŽAX76 ` 4%>\AP?D8 ; Hn@: ̣HkH@ Never Set H@ Set Early pP ̾ `@Reset Hn`P % HDiH@Bit Dj#Di @Memory Channel DjPHq$@1098HqHvHHPH@ RegPH@, WrapP@Store seq state V@ mostly 1'sP@ mostly 0'sJH@Test@Index HAddress CounterMeasurement Complete Trace PointI‚w‘’“DDQD+B-3D3B3K˃A”’D•DtDK“AP OllKˊB[Kc3[oK̋…oKzVV@AU U ”˜zC™šqzCFt@zCq“4E4DP貗<F›œ;G›š”Bq-:t@*q“P粗.F›œ-G’œ‘”zu˜zC™šqzCD0 Kt@0XozCq“HOmwðy|H@1 @2 @3 @ Time enable @ Time resetH@4 ŽAﰬ HnHk Prescale TCC?@ ?4?`aaa aJ‚B3EwxDDl)D D wˆDlA6wˆDDKBlC3„D{ C †{qB3Db3DDKKы|9F…DwˆDBCPQD[DzLwˆzLDJwˆD zKDA„DDBD?zDBD;tDBD5wˆjDzLDDAPD'{_D zKDDAPD„DDBPDlNDqDDAPlPrGB5`PQ& '(E33l %''BD*D'D&D%;B3%'PQDP`DPPADP`PD '(HҰ '(IӰc3A0PEE(@``@?B333΃u7wˆ„ G`3KKo`cCI IPQc3&%&&A6&;%&&A63DCBA6&B%&&(ˏI `PDi@Internal testsDjU@Master[@Trigger U@Storage OKDi@Tests with IMB test board Dj`#HU@Receive 9@Drive :Di@IMB test board limitationsDj`"@(1 = Not tested)U@Drive @Receive @ Enable P`@( HP`@(Port1 pulses,PDC,Port2,Port1,HA$#"U H'@ in slot "DjG L Hk`#PHn@: ̡ H@True H@False  Function never LME,LTE,LSE,HTR)  No IMB test board w‰ARxˆCBt~pOx`x`x`x`x`x`x`x`XV@11 uSec between strobes Ꞑ,``BN' A003qxq`|~C;|~A3Aﳃɐ@ Read address: P@!Write address 0 with walking ones !@: ! !@: ! PB33KCw{~Bx3D3qˆzDŒ[o3QP[oq@LPORTS 1 & 2 and clock cable strobes are driven with Triggers and Trace Point%+16A>@Bank Independence:OA¥DD DDD+BB3QClBFlM¦CCF3§u3JIªNŽAﵐX XAﺒH') XAﺪAﵴ'`@ Data Channel`DjP;HvꞐ*ȵе۵ ԷGrlH,>ff%DGۀBANuTlQKNOGA)X P ̈! ̐PW@Sequence RAMs:@Address @PatternsPDiHqDj Di@3210Dj2Ha@true,Ha@false %$@Data bits: 0 to 3@ 4 to 7@ 8 to 11@12 to 15 @16 to 19PP hLBD DDDD=D^+B;‚w~B3QClBElJDCCE3Dju33K`DbK t:3;DOD3`D[oB3 ;HG3?D@DDK[oD:DD?u APQ'…K[oD3KDKA3DDq„Œ~€DkzGŒ~€„CD7KHDgu{B3G3C33PQ3$/3 }33±C |²DcD  IP3 (D…Gc I3 … I3 &(Cꅺ^""33DDUUffwwPQ A R3DŒuz€NB`@@?ŽAﺊX   '%  HkHnHDiH@Bit Dj&Di`@ Data Channel`DjPHq'Hv+H@zeroes$H@onesH@testH@ counter reset @Store Qualification Address Data all hhphhx `P0?I‚ŠNʷBDDD+DBDelx~D C…~DCICDBlDB3u@ #BXoD ID…BCoDDBD D D|DDwʷDDuIEBtD D QDBDʷQDPDODMDIDCl3DQDMlQIu.QB`PQFBD CDDDFDJDQ3D9D5BDD IGDDQ33D)bͿ[t~D$Q3B3D-IuH…KoBQ0 CPQBC3˷7{N5I0Pu`CB…P`P'&G`GPQSRAmDi@10Dj@- valid data flagsg@Interactive readP_Di@MW1098HqDj@- meas. complete, wrap, address @@ Store enable8@Address counter .@ Wrap controlP(Di@3210Dj@ - data bits @ Null detect @ Data path @RAM testPP ̐  ̐P hhxh hpOPO@DVwxDNwN+BNDDzN~l ~N³N³N{„N׷÷ŷt{D t|Dt~÷73A3B33Ku=<;>RBνAν@ν?νB;… (C…ozhxhxh hK‚G*DD Dro/D jCD.˽|νDGCDfED#ͽ޽ҽFG*GGD hGDͽ޽ԽHA63ˏG" ´…@t6A6BDQDA3D33B3Q3  CPQttA[lQ;tA3[oGF;F ´FFwFFFF{C~|wBz|FB333;3m3˓DDKK˃t9D KD`KKA6B33FzNŷQF +D DF{Š `DD´Pt=Iꅾ2 @ŽAAX ̾@, B9 thru NOR gate Hnp: ̈ ̐P@ Data Path @ Data Storage`7 5@10422 -HPH@upper PH@lower @ Count bits: Di@98Hq@9 Dj@Exclusive or gate DiHDj3210 10474, h hhPFPH‚«DDDEDgFFCnNB3I3¶K loFXQo@`o«4J3D…LN@t8зQD…`¯PQEt9«RD…N@t:BD …~·BD…3˷{„ R`PFt5BDC33«Œˆ3NBvQ}„K[o C3|BFP3cwD  IwDKKoGŽAᅵDiHvDjQ@User data to range RAMs 4H@Range pattern driverH@driverH@ flag storage% I‚«¸¹DD:Dfo 3C3·¬DNDDDDKԃt3¶»KK ldzK2 ~ | ·º½¿ˆNqŠt@t@q¶»I3I3P3FD'¶»FD"º¶»Gl·¬z¿ˆNqŠD0 Kxt@0Xoq¶»HP?cu†ŽAH@1 @2 @3 @ Time enable @ Time resetH@4  HnHk Prescale Ꞑ(A6ľ S4ÇB4ķllĵ§£¤¥lBlAlħ§£AAl4z$4y C4Ę©C§£lx$ A0 A0;4q`qhL||Pqh0PI`q`q`q`qhqhBqaCqiq`qaqa ~(C (CB ?(A,7Al(Rh;B45l -,)(JFE4+l D4(l I4%lH4"lG4§DBy'^`p#A6 S4B4 :ll²³üöúûl uLoLoE4lD4lI4l$0 J1 A03qxq`|~úûüö{Cüpo(K<÷B~øĽøCüöo (D8 O0qxq`qxq`(A8 N0qpqhqpqhĠøCüöoAlęq~~øĒøCüöo(K }(ĄøCüöoHlo Kk(M}|f Lwb(JPt s4e Cp~`IltCi]{CüpovV²³üöúûokulLúûüöo8(JPul$;B#|42{ C4-5øCüöoL+PI$ A003qxq`|~!øCüöo9B4µ²ü³ By`^pqrsA6 S4B4 :ēllđđUT~|x{luĆLoLoE4lD4y{lor$q4o n(PHz$b4cy C4^YyC~|PW0(A8 Jl#8qxq`|~Bqa Kq`Cq`q` ~(C qa<;(Jd7ð4*ll:qxq`|~Bq`q`q`q`Cqaq`wq`l p(Rl;BiI4odEy` $ A4 4B44ĐĎĐCz$b4cy C4^YyC~|PW0(A8 Jl#8qxq`|~Bqa Kq`Cq`q` ~(C qa<;(Jd7ð4*ll:qxq`|~Bq`q`q`q`Cqaq`wq`l p(RP_bȔrč>Aӛ+hjjɐ3ǀ VZΠ롳ugן+)*ȓ,W堈H3/[=P̒q°랐&0ߐF>82" N PR@B$<T6ݬ쬿78㬀4eMJy깩к,ƹԐ.LXD:Hټἱ'\(ɨ N pPpP@ ADRS DEVICE eC74A "Ae|tiyh_*oAAA AA  ADAAPu>AD?(AAo@>@`DLSUIKEGHJYl^D9ET A6D} ؾ؃8/10 MHz State Controller 64621A STATE-CTAABBDEHIKLOL8 0BBBBѷA6 (CB|BC3|A6F0O3η|~XolR4A6DG\oB@?C aA6GGG}G|oCaؓ $$""&&ؤ?ث@BDFACEGA6GqDOPuPu7GzػlD%3D`PE7g7B7LJP@0PI`'7PB'7GOGjئGvثGNo]PQ'4GDGoGEGTCPE0gw Pt@v`lt@ vBlB7G$G?ئG%G4"Bece'-``@?TA6PE'FB77u7FG 1G6FFBPB`OOoAt6&D &DD9EA)Z@`uHIgy^`pqrsbZd'0eђ>e<>m<йPT!~}\\ ] v!)1@lLeӁDk3ҕҕBӧʠVҖҖAӦB 8<@A,D:General Purpose Preprocessor 64650A L]l}ȑȦȵ!Clock / Data Channel VerificationControl / Status Verification!Interface Module I/O Verification'Rising Edge Setup and Hold Verification(Falling Edge Setup and Hold Verification Triggers, Trace Point output &Sequencer, Measurement Complete output 3Interface Module I/O Verification Failed: 0 7`bUUUU""``GEDBD~DEDA73FD(˷@t>A6cDHDE00ju;qx lqx`HXo;lD D3DoDoE0 }(A; j#րP˳ C0 jSPQBB3;lD oD o#4BCA3C333Di3B3D;DDBDDzCDK :2DrKERoO333DhC3B3`P3DDfBDpDRDaCDkDMK :-DMKGBo33PE$$ A|S3T3lS3T3PE#$ A|c3lc3UUeUZUZUUj@@`P3`P3AtGlGGc3"t@lAuGGGoGGGol&π AA3A҄C3llDAoDAʽo3&,3+P /@Pod "@: 7P ͈ @Pod "@: %K D3  0P0 DiHqDj/DiHqDjP@Clock Edges, Positive: &@ Negative: P@Clock Qualifiers, High: +@Low:```````````` @CBDCDEDGDHDIDJDDDD%B`÷D0D i( ; P(; @ Pass Hn`  b @ Pass Hn`  YX`  @ acq bd not present Al@l?B; '(X(C;T3DR@4 Addr 1 Addr 2 Addr 3 Addr 4 Addr 5 Addr 6DSP>@Latch Read/Write@ ECL Hi Value@| *@Clock 5 EnableP@Halt Request Circuitry@| *@Clock 4 EnableP@Interrupt Request Circuitry @| *@Clock 2 EnableP@Status Latch Control@| *@Clock 3 EnableP@Address Latch Control @| *@Control By Interrupt AckDR@19 -- Pod 1 Data -- 0 DUDR@19 -- Pod 2 Data -- 0 DU7DR@19 -- Pod 3 Data -- 0 DU)@CLK 7 @CLK 6 (@CLK 5 ;@CLK 4 P@CLK 3 @CLK 2 (@CLK 1 ;@CLK 0 ' DC' D$,4'4' '0P0PE$|T4T4lT4T 4ma""dDDUUiUZUZUUPh' C%!4DGBM5\]ZlW2* **}8 **o' C$GlJ5A '(CBGl '(CCGl ' CPI]/oBHAҾ'5! C,݈=,܈=ADGGD=' CGnt@䇙PtAҰA҄XC5)+5)G' j5%Gll 5 DA" o5D A  oA+$4BC4 4ҢBGrGtll2Uo@`DLSUIKEGHJYl^clock, TTL threshold @WARNING - NO CLOCKS pPock, TTL threshold @WARNING - NO CLOCKS pPC``ZY%*&&t8^̖̕ țțțʖțț GP ProbesClock: 64636A, Data: 64635A=MbxȇClock/Data channel verification)Set up and hold verification, rising edge*Set up and hold verification, falling edge Triggers, Trace Point output &Sequencer, Measurement Complete output Ȟ""`GDDLDo0RqpXo)uABD#D 00jqx`HXoEElD D3DoDoD CPQB;EElD oD o#4BCA3C333D3B3D;DDBDDzCDK :2DrKEo333DhC3B3`P3DDfBDpDRDaCDkDMK :-DMKGBo33PE$$ A|S3T3lS3T3PE#$ A|c3lc3UUɸUZUZUUɽ@@`P3`P3AtGlGGc3"t@lAuGGGoGGGol' A63AC3DDllDAoDAo3&3+P /@Pod "@: 7P ͈ @Pod "@: %1K D3%̈<@Recommendation: @Unhook Probe Leads  0P0 DiHqDj/DiHqDjP@Clock Edges, Positive: &@ Negative: P@Clock Qualifiers, High: +@Low:' DC' D$,4'4' '0P0PE$|T4T4lT4T 4ʽ""DDUUUZUZUUPh' C%!4DGBM5\]ZlW2* **}8 **o' C$GlJ5A '(CBGl '(CCGl ' CPI]/oBHA'5! C,݈=,܈=AˠGGD=' CGnt@ׇPtA AXC5)+5)G' j5%Gll 5 DA~ho5D A|hoAy+$4BC4 4BGrGtll2UoPH#H'PH#H'P H#H'PH#H'P HC?Dq3S3[oqA̶0rmnC3@:Measure delay from rising edge of any clock, TTL threshold @WARNING - NO CLOCKS pPCGq3nS3[oqA̶0@:Measure delay from rising edge of any clock, TTL thresholdCGCt@t@t@3qA̶X@!Connect clock input to BNC PORT 1 R@%PORT 1 is driven with sequence events pPCGq3nS3[oqA̶0@:Measure delay from rising edge of any clock, TTL thr 0fR&DN.,$ 28*(2KF *(@o@>@`DLSUIKEGHJYl^D9EA)Z@`uHIgy^`pqrsbZd[\^ ]_^` _a`b acbd cedf egfh gihj ikjl kmln monp oqpr qsrt sutv uwvx wyxz y{z| {}|~ }~    ! ! " "