LDY LLRA2 GET FAIL FLAG JSB ERMS,I AND REPORT DEF E165 SPC 2 LOVR1 LDA LRAD3 PUT NEXT RETURN ADDRESS STA M5LNK IN VIOLATION LINK ADDRESS JSB PMONU PM ON W/USER ENABLED DJP *+2 TRY TO DISABLE MEM JSB OFFPM MADE IT W/NO VIOLATION LDY OFFPM GET FAIL FLAG JSB ERMS,I AND OUTPUT DEF E166 SKP LLRA3 NOP JSB TRNOF OFF INT AND USER JSB PIVCK CHECK VIOLATION BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E167 LDA LRAD4 NEXT INTP STA M5LNK ADDRESS JSB PMON NOP CHANGE TO JMP *-N FOR LOOP/ JSB OFFPM TURN OFF PROTECTED MODE JMP LOVR2 AND JUMP OVER THE ERROR LLRA4 NOP JSB TRNOF OFF INTP AND USER LDY TRNOF JSB ERMS,I DEF E200 SPC 2 LOVR2 LDA LRAD5 NEXT ADDRESS STA M5LNK INTO-LINK JSB PMONU PM W/USER ENABLED DJS *+2 DISABLE AND JSB NOP JSB OFFPM JSB MUST HAVE WORKED LDY OFFPM JSB ERMS,I DEF E201 SPC 2 LLRA5 NOP RETURN FROM VIOLATION INTERRUPT JSB TRNOF OFF PROTECTED MODE JSB PIVCK AND CHECK VIOLATION BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E202 LDA LRAD6 UPDATE THE STA M5LNK LINK WORD JSB PMON ON PM W/SYSTEM ENABLED NOP CHANGE TO JMP *-N FOR LOOP/ DJS *+2 NOW MAKE SURE DJS CAN BE NOP EXECUTED IN PM WITH SYS ENABLED JSB OFFPM TURN OFF THE PROTECTED MODE JMP LOVR3 AND JUMP OVER THE ERROR ROUTINE LLRA6 NOP VIOLATION RETURN ADDRESS JSB TRNOF OFF INTP + SYS MAP LDY TRNOF JSB ERMS,I DEF E203 SKP LOVR3 LDA LRAD7 UPDATE STA M5LNK RETURN ADDRESS JSB PMONU PM ON W/USER ENABLED SJP *+2 TRY TO TURN SYSTEM MAP ON JSB OFFPM MADE IT, LDY OFFPM JSB ERMS,I DEF E204 SPC 2 LLRA7 NOP JSB TRNOF OFF INTP, JSB PIVCK AND CHECK VIOLATION REGISTER 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E205 LDA LRAD8 UPDATE STA M5LNK M5LNK JSB PMON ONE PM SJP *+2 SJP JSB OFFPM OK, ITS DONE, OFF PM JMP LOVR4 AND JUMP OVER THE ERROR LLRA8 NOP JSB TRNOF OFF INTP + SYSTEM LDY TRNOF JSB ERMS,I DEF E206 SPC 2 LOVR4 LDA LRAD9 UPDATE STA M5LNK M5LNK JSB PMONU ON PM W/USER ENABLED SJS *+2 ATTEMPT SJS NOP INSTRUCTION JSB OFFPM MADE IT, LDY OFFPM JSB ERMS,I DEF E207 SKP LLRA9 NOP JSB TRNOF OFF INTP AND USER, JSB PIVCK AND CHECK BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E210 LDA LRA10 UPDATE STA M5LNK THE M5LNK JSB PMON ON PROTECTED MODE, SJS *+2 AND JSB NOP JSB OFFPM OK, TURN PM OFF JMP LOVR5 AND JMP OVER THE ERROR LLR10 NOP JSB TRNOF OFF INTP AND SYSTEM LDY TRNOF JSB ERMS,I DEF E211 SPC 2 LOVR5 LDA LRA11 UPDATE STA M5LNK M5LNK JSB PMONU ON PM UJP *+2 TRY UJP WITH PM JSB OFFPM MADE IT, LDY OFFPM JSB ERMS,I DEF E212 SPC 2 LLR11 NOP JSB TRNOF OFF INTP JSB PIVCK CHECK BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E213 LDA LRA12 UPDATE STA M5LNK M5LNK JSB PMON ON PM UJP *+2 NOW ENABLE THE USER MAP RSB READ STATUS JSB OFFPM TURN OFF PROTECTED MODE LDA B PUT STATUS IN A AND BIT12 STRIP ALL BUT BIT12 SZA WAS BIT 12 A ONE? JMP LOVR6 YES, OVER THE ERROR JSB ERMS,I NO, TELL OPERATOR DEF E214 LLR12 NOP JSB TRNOF OFF INTP LDY TRNOF JSB ERMS,I DEF E215 SKP LOVR6 LDA LRA13 UPDATE STA M5LNK M5LNK JSB PMONU ON PM W/USER ENABLED UJS *+2 ATTEMPT EXECUTION OF UJS NOP MUST HAVE MADE IT, JSB OFFPM OFF PM LDY OFFPM JSB ERMS,I DEF E216 SPC 1 LLR13 NOP JSB TRNOF OFF INTP AND USER JSB PIVCK CHECK BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E217 LDA LRA14 UPDATE STA M5LNK M5LNK JSB PMON ON PROTECTED MODE UJS *+2 NOW ENABLE THE USER NOP RSB GET STATUS JSB OFFPM AND FORCE PM OFF LDA B GET STATUS AND MAKE AND BIT12 SURE THAT THE USER SZA MAP WAS ENABLED JMP LOVR7 IT WAS, GO ON JSB ERMS,I NO, TELL OPERATOR DEF E220 JMP LOVR7 THEN GO ON SKP LLR14 NOP JSB TRNOF OFF INTP LDY TRNOF JSB ERMS,I DEF E221 SPC 1 LOVR7 NOP LDA KRT07 NEXT RETURN STA M5LNK ADDRESS LDA KFTRY JSB PMONU ON THE PROTECTED MODE LFA IN PM. JSB OFFPM LDY OFFPM JSB ERMS,I DEF E224 SPC 1 KRA07 NOP JSB TRNOF OFF INTP AND SYSTEM MAP JSB PIVCK CHECK BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E225 NOP JMP TST13,I SKP LRAD1 DEF LLRA1 LRAD2 DEF LLRA2 LRAD3 DEF LLRA3 LRAD4 DEF LLRA4 LRAD5 DEF LLRA5 LRAD6 DEF LLRA6 LRAD7 DEF LLRA7 LRAD8 DEF LLRA8 LRAD9 DEF LLRA9 LRA10 DEF LLR10 LRA11 DEF LLR11 LRA12 DEF LLR12 LRA13 DEF LLR13 LRA14 DEF LLR14 LLSTS OCT 0 SPC 2 E163 ASC 5,E163 JRS/ E164 ASC 5,E164 JRS/ E165 ASC 5,E165 JRS/ E166 ASC 5,E166 DJP/ E167 ASC 5,E167 DJP/ E200 ASC 5,E200 DJP/ E201 ASC 5,E201 DJS/ E202 ASC 5,E202 DJS/ E203 ASC 5,E203 DJS/ E204 ASC 5,E204 SJP/ E205 ASC 5,E205 SJP/ E206 ASC 5,E206 SJP/ E207 ASC 5,E207 SJS/ E210 ASC 5,E210 SJS/ E211 ASC 5,E211 SJS/ E212 ASC 5,E212 UJP/ E213 ASC 5,E213 UJP/ E214 ASC 5,E214 UJP/ E215 ASC 5,E215 UJP/ E216 ASC 5,E216 UJS/ E217 ASC 5,E217 UJS/ E220 ASC 5,E220 UJS/ E221 ASC 5,E221 UJS/ E222 ASC 5,E222 XMA/ E223 ASC 5,E223 XMA/ E224 ASC 5,E224 LFA/ E225 ASC 5,E225 LFA/ KFTRY OCT 100001 HED MAP VIOLATION * * TST14 * * TEST 14 VERIFIES PROPER OPERATION OF THE HARDWARE AND FIRMWARE * REQUIRED TO DETECT AND REPORT THE ATTEMPT, AND PREVENT THE * EXECUTION OF ANY MEM INSTRUCTION WHICH ALTERS THE CONTENTS OF * THE MAPS WHILE IN PROTECTED MODE. * * THIS TEST IS MADE UP OF SEVEN SUBTESTS WHICH ATTEMPT TO ALTER * THE CONTENTS OF THE MAPS, AND THEN INSURE A MEM VIOLATION * AND THE CORRECT STATE OF THE VIOLATION REGISTER'S PRIVILEGED * INSTRUCTION BIT. * * THE INSTRUCTIONS USED TO ATTEMPT ALTERING THE MAPS IN THIS * TEST ARE: * * XMM XMS XMA SYA USA PAA PBA * * IF AN ERROR IS DETECTED DURING THE EXECUTION OF THIS TEST, AN * ERROR MESSAGE IS OUTPUT ON THE CONSOLE, AND THE PROGRAM HALTS * THE COMPUTER. AT THIS TIME, THE OPERATOR MAY DETERMINE THE * CAUSE OF THE ERROR BY CHECKING THE T REGISTER, WHICH CONTAINS * THE ERROR CODE, AND THE Y REGISTER, WHICH CONTAINS THE ADDRESS * OF THE ERROR * * SKP TST14 EQU * SPC 1 NOP JSB KFNCE LOAD FENCES FOR THIS TEST JSB JLOAD LOAD MAPS JSB ZORCH PUT JSBS IN MEMSC AND DVICE SPC 1 LDA MRTD1 PUT INTERRUPT RETURN ADDRESS STA M5LNK IN THE VIOLATION RETURN ADDRESS JSB PMON ON PROTECTED MODE CLA TRY TO LDB MLPTR EXECUTE LDX OCT01 AN XMM XMM INSTRUCTION JSB OFFPM MODE IT, OFF PM LDY OFFPM JSB ERMS,I DEF E226 SPC 1 MRAD1 NOP JSB TRNOF OFF THE INTP AND USER JSB PIVCK CHECK VIOLATION REGISTER BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E227 LDA MRTD2 UPDATE THE STA M5LNK RETURN ADDRESS CLA NOW CLB TRY LDX OCT40 EXECUTING JSB PMON XMS XMS IN PM JSB OFFPM MADE IT, OFF PM LDY OFFPM JSB ERMS,I DEF E230 SKP MRAD2 NOP JSB TRNOF OFF INTP AND SYS JSB PIVCK CHECK BIT12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E231 LDA MRTD3 UPDATE STA M5LNK M5LNK LDA MLPTR POINT TO JLOAD TABLE JSB PMON TURN PM ON SYA TRY TO LOAD SYSTEM MAP JSB OFFPM LDY OFFPM JSB ERMS,I DEF E232 SPC 1 MRAD3 NOP JSB TRNOF OFF INTP AND SYS MAP JSB PIVCK CHECK PI VIOLATION BIT JMP *+5 LDY PIVCK JSB ERMS,I DEF E233 LDA MRTD4 UPDATE STA M5LNK M5LNK LDA MLPTR NOW JSB PMON TRY USA USA JSB OFFPM OFF PROTECTED MODE LDY OFFPM JSB ERMS,I DEF E234 SPC 1 MRAD4 NOP JSB TRNOF OFF THE INT SYS JSB PIVCK AND CHECK BIT12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E235 LDA MRTD5 UPDATE STA M5LNK M5LNK LDA MLPTR NOW JSB PMON ATTEMPT PAA PAA IN PM JSB OFFPM LDY OFFPM JSB ERMS,I DEF E236 SKP MRAD5 NOP JSB TRNOF OFF INTP AND SYS JSB PIVCK CHECK BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E237 LDA MRTD6 UPDATE STA M5LNK THE LINK WORD LDA MLPTR NOW JSB PMON TRY A PM ON PBA PBA JSB OFFPM LDY OFFPM JSB ERMS,I DEF E240 SPC 1 MRAD6 NOP JSB TRNOF OFF INTP JSB PIVCK AND CHECK BIT 12 JMP *+5 LDY PIVCK JSB ERMS,I DEF E241 SPC 1 LDA KRT05 UPDATE VIOLATION STA M5LNK RETURN ADDRESS LDA KXFRW GET TRANSFER WORD NOP CHANGE TO JMP *-N FOR LOOP/ JSB PMON ON THE PROTECTED MODE XMA TRY XMA INSTRUCTION JSB OFFPM MUST HAVE MADE IT, LDY OFFPM GET FAIL FLAG JSB ERMS,I REPORT THE ERROR DEF E222 SPC 1 KRA05 NOP INTERRUPT RETURN ADDRESS JSB TRNOF OFF THE INTP AND SYSTEM JSB PIVCK CHECK BIT 12 JMP *+5 OK GO ON LDY PIVCK NO, GET FAIL FLAG JSB ERMS,I AND REPORT NO BIT 12 DEF E223 NOP JMP TST14,I SKP E240 ASC 5,E240 PBA/ E241 ASC 5,E241 PBA/ SPC 2 MRTD1 DEF MRAD1 MRTD2 DEF MRAD2 MRTD3 DEF MRAD3 MRTD4 DEF MRAD4 MRTD5 DEF MRAD5 MRTD6 DEF MRAD6 MLPTR DEF LTSYS HED MEM DIAGNOSTIC - DCPC INTERFERENCE TEST * * TST20 * * TEST 20 VERIFIES PROPER OPERATION OF THE HARDWARE AND FIRMWARE * REQUIRED TO SUCESSFULLY LOAD AND READ MAP REGISTERS WHILE * EXECUTING DCPC TRANSFERS. * * THIS TEST IS COMPRISED OF EXECUTING A USA AND USB WHILE DCPC * IS TRANSFERING DATA, AND CHECKING THE RESULTS. IF NO * ERROR IS FOUND FOR EVERY COMBINATION OF MAP REGISTER LOAD, * THE TEST IS EXITED. * * IF AN ERROR IS DETECTED DURING THE EXECUTION OF THIS TEST, * AN ERROR MESSAGE IS OUTPUT ON THE CONSOLE, AND THE PROGRAM * HALTS THE COMPUTER. THE OPERATOR MAY THEN DETERMINE THE * CAUSE OF THE ERROR BY CHECKING THE FOLLOWING REGISTERS: * * T REGISTER = HALT CODE * A RESISTER = ACTUAL PATTERN * B REGISTER = EXPECTED PATTERN * X REGISTER = FAILING REGISTER * Y REGISTER = ADDRESS OF FAILURE * * * * HED DCPC INTERFERENCE TEST TST20 EQU * SPC 1 NOP JSB LODUP LOAD THE SYSTEM MAP REGISTERS SPC 1 LDY NEG04 LDB LTSYS * QHREB LDX NON07 MAKE A LDA OCT10 LOAD QHREA STA B,I TABLE INA TO DO INB LARGE ISX DCPC JMP QHREA TRANSFERS ISY * JMP QHREB * SPC 1 LDA LTSYS LOAD PAA PORT A AND LDA LTSYS PORT B PBA MAP REGISTERS SPC 1 NOP HEREB LDA PTBCW OTA .DMA7 CLC .DMA3 LDA TWNTK IOR INPCW OTA .DMA3 STC .DMA3 LDA NG31K OTA .DMA3 SPC 2 NOP SJP *+2 QQIO1 STC DVICE,C STC .DMA7,C NOP CLA HEREA JSB CHTBL MAKE SEQUENCE TABLE LDA RTSYS MAKE THE IOR INPCW READ POINTER LDB LTSYS GET THE LOAD POINTER USB LOAD THE MAP AND NOP USA READ 'EM BACK NOP CHANGE TO JMP *-N FOR LOOP/ LDA RTSYS NOW LDB LTSYS COMPARE THE JSB TBCMP TWO TABLES JSB DMAER WHOOPS, DCPC AFFECTED USA SFS .DMA7 JMP HEREA NO, DO ANOTHR USA NOP JMP HEREB YES, DO ANOTHER DCPC SETUP SPC 5 CHTBL NOP LDA HOLDR GET LAST COUNT LDY NON40 LDB LTSYS AND POINTER XXXQQ INA BUMP REGISTER PATTERN CPA LAST TIME TO RESET? JMP EXITQ STA B,I NO, PUT IT IN THE TABLE INB BUMP POINTER STA HOLDR SAVE THE PATTERN ISY BUMP THE XTHRU JMP XXXQQ KEEP GOING JMP CHTBL,I DONE, EXIT SPC 1 DMAER NOP DJS RGSVE DISABLE MEM AND SAVE THE REG. LDY DMAER JSB ERMS,I DEF E264 JMP TCPHR SJS RGRS2 REENABLE AND RESTORE Y SPC 2 WAITQ LDA QFLAG SZA,RSS JSB QRASH DCPC NOT COMPLETE AFTER 2 SEC CLA FIRST TIME THRU STA QFLAG RESET QFLAG LDA OCT2K OFF TO JSB TMRR,I 2 SECOND TIMER JMP .EXTQ AND DO SFS 7 AGAIN SPC 1 QRASH NOP LDY QRASH GET FAIL FLAG CLC INTP,C DJP *+2 NO DCPC FLAG, CRASH JSB ERMS,I DEF E267 JMP TST.Q E267 ASC 5,E267 DCPC/ SKP EXITQ CCA STA QFLAG .EXTQ SFS .DMA7 JMP *+2 JMP TST.Q JMP WAITQ SPC 2 TST.Q DJP *+2 CLC INTP,C NOP JMP TST20,I SPC 1 HOLDR OCT 0 LAST OCT 1777 PTBCW OCT 100014 .DMA7 EQU 7B .DMA3 EQU 3B INPCW OCT 100000 NG31K OCT -31000 NON07 OCT -7 NEG04 OCT -4 QFLAG OCT 0 E264 ASC 5,E264 DCPC/ HED INTERRUPTIBLE INSTRUCTIONS TEST * * TST17 * * TEST 17 VERIFIES PROPER OPERATION OF THE HARDWARE AND FIRMWARE * REQUIRED TO COMPLETE THE EXECUTION OF AN INSTRUCTION WHICH HAS * INTERRUPTED BY THE CPU. * * TEST 17 IS MADE UP OF EIGHT SUBTESTS WHICH START EXECUTION OF * AN INTERRUPTIBLE INSTRUCTION, AND THEN CAUSE AN INTERRUPT. * AT THE COMPLETION OF THE INTERRUPT HANDLING ROUTINE, CONTROL * IS RETURNED TO THE INTERRUPTED INSTRUCTION, AND THEN THE * RESULTS OF THE INSTRUCTION UNDER TEST ARE CHECKED TO VERIFY * COMPLETION. * * THE INSTRUCTIONS TESTED ARE: * * MBF MBI MBW MWF MWI MWW XMS XMM * * IF AN ERROR IS DETECTED DURING EXECUTION OF THIS TEST, AN * ERROR MESSAGE IS OUTPUT ON THE CONSOLE, AND THE PROGRAM HALTS * THE COMPUTER. AT THIS TIME, THE OPERATOR CAN DETERMINE THE