HED TEST 07 * * * TEST 07 * ------- * THIS TEST CHECKS THE CONCATENATED CLF WITH MIA/B, * LIA/B AND OTA/B INSTRUCTIONS. * TST07 EQU * NOP JSB T07 CLC INTP,C JMP TST07,I * T07 NOP CLC INTP,C TURN OFF ALL I/O LDA .+1 TEST OVERFLOW REG JSB T7TCS LDA LSC TEST CLF ON 1. INTF. BOARD JSB T7TCS JMP T07,I * * * SUBROUTINE TO CONFIGURE I/O INSTR & EXECUTE INSTR * WITH CLF ATTACHED. * T7TCS NOP STA T4SC STORE & CONFIGURE SC OF I/O INSTR LDB T7CPT JSB ISC CLA SET ERR FLAG TO 0 STA T7EFG T7.01 STF CH MIA CH,C TEST CLF CONCATENATED TO MIA JSB T7TST MIB CH,C " " " " MIB JSB T7TST LIA CH,C " " " " LIA JSB T7TST LIB CH,C " " " " LIB JSB T7TST OTA CH,C " " " " OTA JSB T7TST OTB CH,C " " " " OTB JSB T7TST JMP T7TCS,I * SKP * * SUBROUTINE TO TEST FLAG & OUTPUT ERROR MESSAGE * T7TST NOP T7.02 SFC CH CHECK IF FLAG WAS CLEARED JMP *+4 NO, ERROR STF CH YES, OK. SET FLAG FOR NEXT CHECK & ISZ T7EFG INCREMENT ERR FLAG JMP T7TST,I * LDA T7EFG DETERMEN MEM LOG OF STORED I/O INSTR ALS ASCII STRING BY CALCULATING: ADA .+4 (ERR FLAG * 2) + 4 + START ADDRESS LDB ER51P,I ADA B LDB A,I LOAD B-REG WITH 1.& 2. ASCII STRING & STB ER42+3 STORE IN ERR MESSAGE INA LDB A,I STB ER42+4 * LDA T4SC CONVERT FAILING SC JSB N2AO STA ER42+5 * E042 JSB ERMS,I PRINT ERR MESSAGE DEF ER42 ISZ T7EFG INCREMENT ERR FLAG JMP T7TST,I * * ER42 ASC 18,E042 XXX YY,C FAILED TO CLEAR FLAG/ * ER51P DEF ER51 T7EFG OCT 0 * T7CPT DEF *+1 * DEF T7.01 DEF T7.01+1 DEF T7.01+3 DEF T7.01+5 DEF T7.01+7 DEF T7.01+9 DEF T7.01+11 DEF T7.02 DEF T7.02+2 DEC -1 * * * *************************************************************** SKP HED TEST 08 * * * TEST 08 * ------- * THIS TEST CHECKS THE SPECIAL SWITCHING CAPABILITIES * OF EITHER ONE 12979B EXTENDER UNDER PROGRAM CONTROL * OF TWO CPU'S, OR TWO I/O EXTENDERS UNDER PROGRAM * CONTROL OF ONE CPU. DURING CONFIGURATION OF THE * DIAGNOSTIC THIS TEST MUST BE SELECTED WITH THE HELP * OF S-REG BIT 15. IF THIS TEST IS SELECTED TESTS * 00 - 07 CAN NOT BE EXECUTED. * * ORG 6000B TST08 EQU * NOP JSB T08 CLC INTP,C JMP TST08,I * T08 NOP CLC INTP,C TURN OFF ALL I/O JSB CPTYP CHECK IF 21MX OR 21XE LDA BSSC1 CONFIGURE BUS SWITCH SC1 LDB BSCP1 JSB ISC LDA BSSC1 TRANSFER CURRENT BASE SC STA BSSCX INTO BUFFER * LDA USSC IS TEST REQUESTED ON REDUNDANT CPU'S? RAL SSA JMP EXTST NO, REDUNDANT EXTENDERS * SKP * * * *** TEST ONE EXTENDER CONNECTED TO TWO REDUNDANT CPU'S *** * * LDA .-4 SET LOOP COUT TO -4 STA T8CNT CPU01 STC BSC1 GET SWITCH LDA T5S LOAD TIME CONSTANT (5 SEC) JSB DAFSR GO TO FLAG, DATA CHECK & WAIT SUBROUT. JMP CPUNT TRANSFER DID NOT TIME OUT * * * TRANSFER TIMED OUT ON THIS CPU. THIS IS EITHER "CPU#2" * OR STC 7X FROM OTHER CPU DOES NOT WORK * LDA SW11 LOAD A TIME CONSTANT OF 2 SEC & GO TO JSB DAFSR FLAG, DATA CHECK & WAIT SUBROUTINE JMP FL08A SWITCH TAKEN BY OTHER CPU BEFORE 2 SEC E044 JSB MSGC,I TIME OUT ERROR, OTHER CPU DID NOT TAKE DEF ER44 SWITCH OR STC 7X ON OTHER CPU DID LDA CW02 NOT WORK (WILL OUTPUT E044 JSB FLDTC FOLLOWED BY E043) * FL08A LDA .+10 WAIT 10 MSEC TO ALLOW OTHER CPU TO JSB TMRR,I TEST ITS CAPABILITY TO GET THE CPU02 STC BSC1 SWITCH, THEN TAKE SWITCH & CHECK LDA CW01 IF RECEIVED JSB FLDTC JSB T08RC GO TO INFINITE WAIT LOOP FOR RESINC * ** STC 7X WORKS FROM BOTH CPU'S. TEST CLF 7X INSTR. ** * LDA CW04 CHECK IF OTHER CPU'S CLF INSTR DID NOT JSB FLDTC THROW SWITCH TO THIS CPU (<130 MSEC) LDA .+1 WAIT 1 MSEC TO LET OTHER CPU REACH JSB TMRR,I WAIT LOOP CPU03 STC BSC1 TAKE SWITCH TO RESINC BOTH CPU'S * CPU08 CLF BSC1 THROW SWITCH TO NEUTRAL POS.& CHECK LDA CW03 THAT SWITCH IS NO MORE CONNECTED TO JSB FLDTC THIS CPU (< 130 MICROSEC) * ** CLF 7X WORKS FROM BOTH CPU'S. TEST CLC 7X INSTR ** * LDA .+1 WAIT 1 MSEC TO LET OTHER CPU REACH JSB TMRR,I 2 MSEC WAIT LOOP, THEN TAKE SWITCH CPU09 STC BSC1 & GO TO WAIT LOOP FOR RESINC JSB T08RC LDA .+2 WAIT 2 MSEC BEFORE CHECKING THAT JSB TMRR,I OTHER CPU HAS THROWN SWITCH TO LDA CW06 THIS CPU JSB FLDTC * SKP * CPU12 CLC BSC1 THROW SWITCH BACK & CHECK THAT IT LDA CW05 IS GONE JSB FLDTC * ** CLC 7X WORKS FROM BOTH CPU'S. TEST SFC 7X INSTR ** * LDA .+5 WAIT 5 MSEC TO ASSURE THAT OTHER CPU JSB TMRR,I REACHED WAIT LOOP FOR RESINC CPU13 STC BSC1 RESINC BOTH CPU'S, THEN THROW SWITCH CPU14 CLF BSC1 TO NEUTRAL POS. & CHECK THAT IT IS LDA CW03 GONE JSB FLDTC * LDA SW8 WAIT 0.25 SEC TO ALLOW OTHER CPU TO JSB TMRR,I CHECK THAT SWITCH WAS NOT RECEIVED LDA CW08 CHECK THAT SFC IN OTHER CPU DID NOT JSB FLDTC THROW SWITCH TO THIS CPU * CPU22 STC BSC1 TAKE SWITCH FOR RESINC LDA .+2 WAIT 2 MSEC TO LET OTHER CPU TAKE JSB TMRR,I SWITCH & PUT IT TO NEUTRAL * LDA CW04 CHECK THAT CLF IN OTHER CPU DID NOT JSB FLDTC THROW SWITCH TO THIS CPU CPU17 SFC BSC1 TAKE SWITCH FROM NEUTRAL POS. JSB SKPER ERROR, SHOULD HAVE SKIPPED LDA CW07 CHECK THAT SWITCH WAS RECEIVED JSB FLDTC JSB T08RC GO TO WAIT LOOP FOR RESINC * CPU19 SFC BSC1 TRY TO TAKE SWITCH & CHECK THAT RSS IT WAS NOT POSSIBLE JSB SKPRE ERROR, SHOULD NOT HAVE SKIPPED LDA CW09 CHECK THAT SWITCH NOT RECEIVED JSB FLDTC WITH SFC LDA S1587 WAIT UP TO 0.38 SEC FOR RESPONSE JSB DAFSR FROM OTHER CPU RSS JSB ER50 TIME OUT ERROR * LDA .+1 WAIT 1 MSEC JSB TMRR,I * LDA CW10 CHECK THAT SFC AFTER CLC ON OTHER JSB FLDTC CPU DID NOT TAKE SWITCH * ** SFC WORKS FOR BOTH CPU'S. THIS CPU HAS THE SWITCH & IS * THE LAST ONE TO FINISH. MAKE IT CPU#1 & RETURN. * LDA SW8 WAIT 0.25 SEC BEFORE RESINC JSB TMRR,I * SKP CPU23 CLC BSC1 WAIT 2 MSEC TO LET OTHER CPU LDA .+2 CHECK CLC AGAIN, THEN TAKE SWITCH JSB TMRR,I BACK AND RETURN TO LOOP WITH CPU25 STC BSC1 10 MSEC TIME OUT LDA .+10 ISZ T8CNT INCREMENT LOOP COUNT RSS JMP NQIP GO TO LAST TEST SECTION JMP CPU01+2 * NQIP JSB NQI TEST UNDEFINED I/O INSTR LDA SW9 WAIT 0.5 SEC TO LET OTHER CPU JSB TMRR,I CHECK UNDEFINED I/0 INSTR JMP T08,I SKP * * TRANSFER DID NOT TIME OUT ON THIS CPU. "CPU#1" * OTHER CPU TOOK EXTENDER AFTER THIS ONE GOT IT OR * STC 7X FROM THIS CPU DOES NOT WORK. * CPUNT LDA T6S LOAD TIME CONSTANT (6 SEC) & WAIT TO JSB TMRR,I ASSURE OTHER CPU TIMES OUT (6 SEC) CPU04 STC BSC1 GET SWITCH, FETCH CONTROL WORD & LDA CW01 CHECK IF SWITCH WAS TAKEN JSB FLDTC * LDA .60 WAIT FOR 48 MSEC TO LET OTHER CPU TIME JSB TMRR,I OUT & TAKE THE SWITCH, THEN CHECK LDA CW02 THAT SWITCH IS GONE JSB FLDTC * ** STC WORKS FROM BOTH CPU'S. TEST CLF 7X INSTR. ** CPU05 STC BSC1 TAKE SWITCH TO RESINC BOTH CPU'S CPU06 CLF BSC1 THROW SWITCH TO NEUTRAL POS. & CHECK LDA CW03 THAT SWITCH IS NO MORE CONNECTED TO JSB FLDTC THIS CPU (< 130 MICROSEC) * CPU07 STC BSC1 TAKE SWITCH TO START RESINC OF BOTH CPU'S JSB T08RC THEN GO INTO WAIT LOOP FOR RESINC LDA CW04 CHECK IF OTHER CPU'S CLF INSTR DID NOT JSB FLDTC THROW SWITCH TO THIS CPU (<130 MICSEC) * ** CLF 7X WORKS FORM BOTH CPU'S. TEST CLC 7X INSTR ** * LDA .+2 WAIT 2 MSEC TO LET OTHER CPU REACH JSB TMRR,I RESINC WAIT LOOP CPU10 STC BSC1 TAKE SWITCH TO RESINC LDA .+1 TIME OUT FOR 1 MSEC TO ASSURE THAT JSB TMRR,I CPU GOT OUT OF SINC WAIT LOOP, CPU11 CLC BSC1 THEN THROW SWITCH TO OTHER CPU LDA CW05 & CHECK THAT IT'S GONE JSB FLDTC LDA .+2 WAIT 2 MSEC JSB TMRR,I * LDA CW06 CHECK THAT SWITCH WAS THROWN TO JSB FLDTC THIS CPU BY OTHER ONE * ** CLC 7X WORKS FROM BOTH CPU'S. TEST SFC 7X INSTR ** * JSB T08RC GO INTO WAIT LOOP FOR RESINC LDA .+1 WAIT 1 MSEC, THEN CHECK THAT JSB TMRR,I SWITCH WAS NOT THROWN BACK LDA CW04 TO THIS CPU JSB FLDTC * CPU15 SFC BSC1 TAKE SWITCH FROM NEUTRAL POS JSB SKPER ERROR, SHOULD HAVE SKIPPED LDA CW07 CHECK THAT SWITCH WAS RECEIVED JSB FLDTC * LDA SW87 WAIT UP TO 0.38 SEC FOR RESPONSE JSB DAFSR FROM OTHER CPU RSS OK JSB ER50 TIME OUT ERROR * CPU24 STC BSC1 CPU16 CLF BSC1 PUT SWITCH TO NEUTRAL POS & CHECK LDA CW03 THAT GONE JSB FLDTC * LDA SW8 WAIT 0.25 SEC TO LET OTHER CPU CHECK JSB TMRR,I THAT SFC IS OK, THEN CHECK THAT LDA CW08 SWITCH WAS NOT THROWN TO THIS JSB FLDTC CPU * CPU18 STC BSC1 RESINC BOTH CPU'S, THEN WAIT 0.25 SEC LDA SW8 JSB TMRR,I LDA CW10 CHECK THAT SFC ON OTHER CPU DID NOT JSB FLDTC TAKE SWITCH FROM THIS CPU * CPU20 CLC BSC1 GIVE SWITCH TO OTHER CPU CPU21 SFC BSC1 TRY TO TAKE IT BACK & CHECK IT IS RSS NOT POSSIBLE (NOT IN NEUTRAL) JSB SKPRE ERROR, SHOULD NOT HAVE SKIPPED LDA CW09 CHECK THAT SWITCH WAS NOT JSB FLDTC RECEIVED WITH SFC * ** SFC WORKS ON BOTH CPU'S. (THIS IS THE 1. CPU TO FINISH. * OTHER CPU HAS THE SWITCH. MAKE THIS CPU#2 & RETURN. LDA S1587 WAIT UP TO 0.38 SEC FOR RESPONSE JSB DAFSR FROM OTHER CPU RSS OK, RESINCED BY OTHER CPU JSB ER50 TIME OUT ERROR * LDA CW06 CHECK AGAIN THAT OTHER CPU COULD JSB FLDTC THROW SWITCH TO THIS CPU LDA .+5 WAIT 5 MSEC BEFORE RETURN JSB TMRR,I ISZ T8CNT INCREMENT LOOP COUNT RSS JMP LTS08 GO TO LAST TEST SECTION JMP CPU01 * LTS08 LDA SW8 WAIT FOR 0.25 SEC, THEN GO TO JSB TMRR,I LAST TEST SECTION JSB NQI JMP T08,I * SKP * * *** TEST TWO REDUNDANT EXTENDERS CONNECTED TO ONE CPU *** * * EXTST LDA .-4 SET LOOP COUNTER TO -4 STA EXCNT JSB DISCO CHECK IF BOTH EXT'S CAN BE DISCON * EXT01 STC BSC1 TAKE SWITCH & CHECK IF RECEIVED LDA CW01 JSB FLDTC * EXT02 CLC BSC1 THROW SWITCH TO OTHER PORT & LDA CW05 CHECK IF GONE JSB FLDTC * EXT03 STC BSC1 TAKE SWITCH & CHECK, THEN THROW LDA CW01 IT TO NEUTRAL POSITION & CHECK JSB FLDTC EXT04 CLF BSC1 LDA CW03 JSB FLDTC * EXT05 SFC BSC1 GET SWITCH & CHECK SKIP CONDITON, JSB SKPER THEN CHECK IF RECEIVED LDA CW07 JSB FLDTC EXT06 CLC BSC1 THROW SWITCH TO OTHER PORT & CHECK LDA CW05 THEN TRY TO TAKE IT & CHECK THAT JSB FLDTC IT'S NOT POSSIBLE & NO SKIP EXT07 SFC BSC1 OCCURED RSS JSB SKPRE LDA CW09 JSB FLDTC * JSB NQI TEST UNDEFINED I/O INSTRUCTIONS * ISZ EXCNT INCREMENT LOOP COUNT JMP EXT01 & REPEAT * LDA EXT01 SEPARATE SC & CHECK IF TEST HAS AND .77 BEEN RUN ON BSC2 CPA BSSC2 JMP T08,I YES, EXIT TEST LDA BSSC2 NO, RECONFIGURE THIS PART OF LDB BSCP2 TEST WITH BUS SWITCH SC2, CHANGE JSB ISC BUS SW SC BUFFER & REPEAT LDA BSSC2 PROCESS ON 2. EXTENDER STA BSSCX JMP EXTST * EXCNT OCT 0 * SKP * CW01 OCT 102421 STC DID NOT CONCT EXT TO THIS CPU CW02 OCT 004421 STC DID NOT CONCT EXT TO OTHER CPU CW03 OCT 003104 CLF DID NOT RELES EXT F. THIS CPU CW04 OCT 002444 CLF CONCTED EXT TO THIS CPU CW05 OCT 003102 CLC DID NOT RELES EXT F. THIS CPU CW06 OCT 102422 CLC DID NOT CONCT EXT TO THIS CPU CW07 OCT 152430 SFC DID NOT CONCT EXT TO THIS CPU, SWCH IN NEUTR CW08 OCT 052450 SFC CONCTED EXT TO THIS CPU, SWCH IN NEUTR CW09 OCT 072450 SFC CONCTED EXT TO THIS CPU, SWCH NOT NEUTR CW10 OCT 173210 SFC RELESED EXT F. THIS CPU, SWCH NOT NEUTR * T8CNT OCT 0 * ER44 ASC 14,E044 THIS CPU TIMED OUT OR/ * * * SUBROUTINE TO PUT CPU IN WAIT LOOP FOR RESINC WITH * OTHER CPU. STAY THERE UNTIL SWITCH IS GONE. * T08RC NOP T8.01 STC CH,C TURN BOARD ON NOP NOP NOP T8.02 SFS CH IS FLAG SET? RSS NO, BOARD TAKEN OR NO FLAG JMP T8.01 YES, BOAD STILL IN POSSESSION T8.17 SFC CH DO WE STILL HAVE BOARD? JMP T08RC,I NO, BOARD TAKEN JSB E045 YES, ERROR * * * * FLAG ERROR FROM INTERFACE BOARD * E045 NOP JSB ERMS,I DEF ER45 JMP T08,I * ER45 ASC 18,E045 FLAG FF STAYS CLEARED ON INTF./ * SKP * * SUBROUTINES FOR SKIP FAILURES OF SFC 7X INSTRUCTION * SKPER NOP SHOULD HAVE SKIPPED BUT DID NOT JSB ERMS,I DEF ER46 JMP SKPER,I * ER46 ASC 20,E046 NO SKIP ON SFC & SWITCH IN NEUTRAL/ * * SKPRE NOP SHOULD NOT HAVE SKIPPED BUT DID JSB ERMS,I DEF ER47 JMP SKPRE,I * ER47 ASC 22,E047 SKIPPED ON SFC & SWITCH ON OTHER PORT/ * * * * TIME OUT SUBROUTINE * ER50 NOP JSB ERMS,I DEF EM50 JMP T08,I * * * * SUBROUTINE TO CHECK THAT CPU IS A 21MX OR 21XE * CPTYP NOP LDA CPTO IS CPU A 21MX/XE? SSA JMP CPTYP,I YES, RETURN JSB ERMS,I NO, OUTPUT ERROR MESSAGE DEF ER52 LDA CPTYP DETERMEN EXIT ADDRESS OF CMA TEST & RETURN TO CONTROL ADA .+3 PROGRAM CMA IOR SW15 JMP A,I * ER52 ASC 15,E052 TEST ILLEGAL ON THIS CPU/ SKP * * SUBROUTINE TO CHECK FLAG & DATA TRANSFER EVERY MSEC * (TIMER ERROR < +5% DUE TO OVERHEAD OF SUBROUTINE) * INPUT: A-REG BIT 15: IF SET: EXIT ROUTINE AS SOON AS FLAG * GETS SET AND DATA TRANSFER SUCCESSFUL * IF CLEARED: EXIT ROUTINE AS SOON AS * FLAG IS NOT SET OR DATA TRANSFER * FAILED. * BIT 14-0: IF ROUTINE DOES NOT EXIT, TIME OUT * AFTER SPECIFIED NUMBER OF MSEC (OCTAL) * OUTPUT: IF TIME OUT WAS REACHED: P _ P+2 * IF EXITED BEFORE TIME OUT: P _ P+1 * DAFSR NOP STA DAF1 STORE INPUTTED VALUE PRELIMINARILY AND P7777 SEPERATE TIMING CONSTANT, 2TH COMPLEM. CMA,INA & STORE STA DAF2 DAFRT LDA DAF1 GET VALUE AGAIN, SEPARATE SWITCH AND SW15 SETTING & STORE STA DAF1 LDB DAF3 LOAD DATA PATTERN & SEND DATA T8.03 OTB CH T8.04 STC CH,C NOP GIVE 12554 BOARD TIME TO REPLY NOP SSA,RSS IS BIT 15 SET? JMP T8.07 NO, IT'S CLEARED * T8.05 SFS CH YES, WAS FLAG SET? JMP *+4 NO T8.06 LIA CH YES, CHECK IF DATA COMPARES ALSO CPA B JMP DAFSR,I FLAG SET & DATA COMPARES, RETURN JMP DACTN FLAG NOT SET OR DATA NOT COMPARE, CONTINUE * T8.07 SFS CH WAS FLAG SET? JMP DAFSR,I NO, FLAG NOT SET, RETURN T8.08 LIA CH YES, CHECK IF DATA COMPARES CPA B JMP DACTN YES, CONTINUE JMP DAFSR,I NO, DATA DOES NOT COMPARE, RETURN * DACTN LDA .+1 WAIT FOR 1 MSEC IN TIMER JSB TMRR,I ISZ DAF2 HAS TIME OUT BEEN REACHED? JMP DAFRT NO, RETRY AGAIN ISZ DAFSR YES, INCREMENT RETURN ADDRESS NOP JMP DAFSR,I & RETURN * DAF1 OCT 0 DAF2 OCT 0 * SKP * * SUBROUTINE TO CHECK FLAG AND/OR DATA TRANSFER TO INTER- * FACE BOARD IN EXTENDER. WHEN THE SUBROUTINE IS ENTERED * A-REG BIT 15 DETERMENS THE EXIT CONDITIONS: * IF SET: CORRECT EXIT FROM SUBROUTINE IF SFS IS MET * IF CLEARED: " " " " " SFC " " * IN CASE OF ERROR A-REG BITS 14-0 DETERMENS THE PIECES * OF THE ERROR MESSAGE WHICH HAVE TO BE CONCATENATED. * * A-REG BITS * 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * ------------------------------------------------------------ * ! NOT ! ! ! F. TO ! ! ! ! SFC SFS CLC STC * ! ! ! THIS CPU ! ! ! DID NOT CONNECT * ! ! OTHER CPU ! ! CONNECTED * ! WITH SWITCH ! DID NOT RELEASE * IN NEUTRAL RELEASED * FLDTC NOP RETURN F. ROUTINE IN < 130 MICROSEC STA T08CW STORE RECEIVED CONTROL WORD SSA SHALL SUBROUTINE CHECK ON SFC? JMP SFSTS NO, ON SFS INSTR. * * CHECK THAT SKIP ON FLAG IS NOT POSSIBLE ON INTF & NO DATA * TRANSFER TAKES PLACE * LDA .1252 YES, LOAD DATA WORD LDB .-5 SET LOOP COUNT TO -5 STB T08B T8.09 OTA CH TRANSFER DATA WORD TO BOARD T8.10 STC CH,C NOP GIVE 12554 BOARD TIME TO REPLY NOP NOP T8.11 SFS CH IS FLAG SET? JMP *+3 NO, BOARD TAKEN OR NO FLAG JSB T08ER YES, ERROR JMP T08,I EXIT TEST T8.18 SFC CH DO WE HAVE BOARD? RSS NO, OK JSB E045 YES, ERROR ISZ T08B YES, INCR. COUNT & RETRY JMP T8.11 T8.12 LIB CH DID DATA COME THROUGH? CPA B RSS YES, ERROR JMP *+3 NO, OK JSB T08ER JMP T08,I EXIT TEST JMP FLDTC,I EXIT AFTER < 130 MICROSEC * SKP * * CHECK THAT FLAG GETS SET ON INTERF BOARD & * DATA TRANSFER TAKES PLACE * SFSTS CLA DATA TRANSFER TO INTERF BOARD WITH JSB SFSST 000000, 177777, 125252 & 525252 CCA JSB SFSST LDA .1252 JSB SFSST LDA .0525 JSB SFSST JMP FLDTC,I EXIT ROUTINE AFTER < 130 MICROSEC * SFSST NOP T8.13 OTA CH TRANSFER DATA TO BOARD T8.14 STC CH,C NOP GIVE 12554 BOARD TIME TO REPLY NOP NOP T8.15 SFS CH DID BOARD REPLY? JSB T08ER NO, ERROR T8.16 LIB CH YES, DOES DATA COMPARE? CPA B JMP SFSST,I YES, RETURN * * DATA TRANSFER ERROR * STA T08A NO, STORE TRANSM. RECEIVED DATA WORD STB T08B CLE CONVERT TRANSM DATA TO ASCII & STUFF IN LDB B56P1 ERROR MESSAGE JSB O2AS,I CLE CONVERT RECEIVED DATA TO ASCII & STUFF LDA T08B IN ERROR MESSAGE LDB B56P2 JSB O2AS,I LDA LSC FETCH SC OF INTERFACE BOARD JSB N2AO CONVERT SC TO ASCII & STUFF INTO ERR MSG STA BE56+13 LDA BSSCX FETCH SC OF BUS SW & STUFF IN MSG JSB N2AO STA BE56+20 LDA T08A RESTORE A & B WITH TRANSM & RECVED DATA LDB T08B & OUTPUT ERROR MESSAGE E056 JSB ERMS,I DEF BE56,I DEF BE561,I DEF BE562 JMP T08,I RETURN TO TEST 08 * SKP