*        THIS TEST CHECKS THE DATA INPUT PACKING
*         CAPABILITY OF THE DMA.
      SPC 3 
T.20  EQU * 
      JSB PKFD
      JMP T.21
      CLA 
      STA FLAG      SET FLAG FOR FIRST PASS 
PKI1  JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLC 0,C       CLEAR ALL DEVICES, INT SYS OFF
      CLA           CLEAR PACKED WORD INPUT 
      STA PWS        STORAGE AREA 
      LDA BYT.U 
      ALF,ALF 
      IOR BYT.L 
      STA PWRD
      LDA BYT.U     PUT WORD TO BECOME UPPER BYTE 
CH38  OTA CH         INTO INPUT BUFFER
      LDB BT5 
      JSB CHKSW,I   TTY?
      JMP *+3 
CH39  STC CH,C
CH40  CLC CH
      LDA APWS      ADDR OF INPUT AREA IN A 
      CCB           -1 IN B 
      JSB IN1,I     READY DMA1
      LDA BT14      CHANGE CTL WRD TO BYTE, NO
      IOR CHA        STC OR CLC 
      OTA 6 
      STC 6,C       TURN ON DMA1
      NOP 
      LDA BYT.L     PUT WORD TO BECOME LOWER BYTE 
CH52  OTA CH         IN INPUT BUFFER & FINISH XFR 
      LDB BT5 
      JSB CHKSW,I   TTY?
      JMP CH75
CH42  STC CH,C
CH43  CLC CH
      RSS 
CH75  STF CH        GENERATE SRQ TO COMPLETE XFR
      NOP 
      SFS 6 
      JSB FLG.1,I * E50. DMA1 FLG NOT SET AFTER XFR 
      LDA PWRD      CHECK PACKED INPUT WORD 
      STA DAOUT 
      CPA PWS       CORRECT?
      JMP PKI2      YES 
      LDB A104A     CORRECT DATA IN A, MSG ADDR IN B
      JSB DATA,I    CONVERT TO ASCII
      LDA PWS       INPUT IN A
      STA DAIN
      LDB A104B     MSG ADDR IN B 
      JSB DATA,I    CONVERT TO ASCII
E104  JSB ERROR,I * DMA1--INPUT BYTE ERROR. GOOD= 
*                                    XXXXXX, BAD=XXXXXX 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      SPC 2 
PKI2  EQU * 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLA           TEST DMA2 
      STA PWS 
      LDA BYT.U 
CH44  OTA CH
      LDB BT5 
      JSB CHKSW,I   TTY?
      JMP *+3 
CH45  STC CH,C
CH46  CLC CH
      LDA APWS
      CCB 
      JSB IN2,I 
      LDA BT14
      IOR CHA 
      OTA 7 
      STC 7,C 
      NOP 
      LDA BYT.L 
CH47  OTA CH
      LDB BT5 
      JSB CHKSW,I   TTY?
      JMP CH80
CH48  STC CH,C
CH49  CLC CH
      RSS 
CH80  STF CH
      NOP 
      SFS 7 
      JSB FLG.2,I * E53. DMA2 FLG NOT SET AFTER XFR 
      LDA PWRD
      STA DAOUT 
      CPA PWS 
      JMP REVRS 
      LDB A106A 
      JSB DATA,I
      LDA PWS 
      STA DAIN
      LDB A106B 
      JSB DATA,I
E106  JSB ERROR,I * DMA2--INPUT BYTE ERROR. GOOD= 
*                                   XXXXXX, BAD=XXXXXX
      JSB H/L,I     CHECK FOR LOOP ON TEST
      JMP REVRS 
      SPC 2 
REVRS EQU * 
      LDA BYT.U     REVERSE CONTENTS
      LDB BYT.L      OF BYT.L & BYT.U 
      STA BYT.L 
      STB BYT.U 
      LDA FLAG
      SZA           WHICH PASS IS THIS? 
      JMP T.21      SECOND
      CCA           FIRST 
      STA FLAG      SET FLAG FOR PASS 2 
      JMP PKI1      REPEAT TEST 
      SPC 2 
BYT.U OCT 252       INITIAL 
BYT.L OCT 125        VALUES 
PWS   BSS 1 
      SKP 
      HED T.21 - ILLEGAL SELECT CODE TEST 
T.21  EQU * 
      CLC 0,C 
* 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLF 6 
      STF 1 
      SFC 6 
E121  JSB ERROR,I * STF 1 SET DMA1 FLG
      JSB H/L,I     CHECK FOR LOOP ON TEST
      SPC 2 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLF 6 
      STF 16B 
      SFC 6 
E122  JSB ERROR,I * STF 16 SET DMA1 FLG 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      SPC 2 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      LIB 1 
      STB SAVB
      STC 2 
      CLA           OUTPUT ZEROS TO WCR 
      OTA 2 
      CCA           ONES IN A 
      OTA 1         WCR SHOULD NOT RESPOND TO SC1 
      LIA 2 
      LDB SAVB
      OTB 1 
      SZA 
E125  JSB ERROR,I * OTA1 SET DMA1 WCR 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      SPC 2 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLA           OUTPUT ZEROS TO WCR 
      OTA 2 
      CCA           ONES IN A 
      OTA 12B       WCR SHOULD NOT RESPOND TO SC12
      LIA 2 
      SZA 
E126  JSB ERROR,I * OTA 12 SET DMA1 WCR 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      JSB CTPD
      JMP END 
      SPC 3 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLF 7         TEST DMA2 
      STF 1 
      SFC 7 
E123  JSB ERROR,I * STF 1 SET DMA2 FLG
      JSB H/L,I     CHECK FOR LOOP ON TEST
      SPC 2 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLF 7 
      STF 17B 
      SFC 7 
E124  JSB ERROR,I * STF 17 SET DMA2 FLG 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      SPC 2 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      LIB 1 
      STB SAVB
      STC 3 
      CLA 
      OTA 3 
      CCA 
      OTA 1 
      LIA 3 
      LDB SAVB
      OTB 1 
      SZA 
E127  JSB ERROR,I * OTA 1 SET DMA2 WCR
      JSB H/L,I     CHECK FOR LOOP ON TEST
      SPC 2 
      JSB SAVAD,I   SAVE LOOP ADDRESS 
      CLA 
      OTA 3 
      CCA 
      OTA 13B 
      LIA 3 
      SZA 
E130  JSB ERROR,I * OTA 13 SET DMA2 WCR 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      HED END ROUTINE 
END   LDB BT10
      JSB CHKSW,I   SUPPRESS NON-ERROR MESSAGES?
      JMP NOEX
      JSB TTSK,I    NO
      LDA AL77
      LDB AM77
      JSB TTY.O,I   END DIAGNOSTIC
NOEX  LDB BT12      IF NO EXEC, RETURNS HERE
      JSB CHKSW,I   HALT AT END OF DIAGNOSTIC?
      RSS 
H77   HLT 77B       DIAGNOSTIC HAS BEEN COMPLETED 
      JMP STRT2 
      HED           *** COMMON SUBROUTINES ***
* 
*        THIS SR RETURNS TO REPORT INTERRUPT ERRORS 
* 
INT.1 NOP           DMA1 INTPT ROUTINE
      CLC 0,C 
      LDA INT.1 
      INA 
      JMP A,I       RETN *+2 & REPORT ERROR 
      SPC 2 
*        THIS SR CHECKS FOR VALIDITY OF SELECT CODE 
*          IN CONFIGURATION. A-REG MUST CONTAIN SC
*          TO BE CHECKED. IF VALID, RETURN TO *+1.
*          IF INVALID, RETURN TO *+2. VALID SELECT
*          CODES ARE 10 - 77 OCTAL. 
      SPC 1 
CHCKI NOP 
      CLB 
CMP   CPA 1         A=B?
      JMP INV         YES 
      INB             NO
      CPB A10 
      JMP CHCKI,I     YES, VALID SC. RETURN *+1 
      JMP CMP         NO
INV   ISZ CHCKI 
      NOP 
      HLT 73B       NO.SELECT CODE INVALID
      JMP CHCKI,I    TURN *+2 
      SPC 2 
* 
* THIS SR CHECKS FOR LOOP ON CURRENT TEST 
* 
H/LI  NOP 
      STA SA.H
      STB SB.H
      LDB BT13
      JSB CHKSW,I   REPEAT TEST?
      JMP REP       YES 
      LDA SA.H      NO
      LDB SB.H
      JMP H/LI,I   RETN *+1 
REP   LDA SA.H
      LDB SB.H
      JMP SAVAI,I   REPEAT
* 
SA.H  NOP 
SB.H  NOP 
      SPC 2 
*        THIS SR SAVES THE ADDRESS OF THE CURRENT 
*          TEST SO THAT TEST MAY LATER BE LOOPED
*          ON BY SETTING SW-REG BIT 13. 
      SPC 1 
SAVAI NOP           LOOP ADDRESS STORED HERE
      JMP SAVAI,I   RETN *+1
      SPC 2 
*        SWITCH REGISTER OPTION CHECKER.
*          CHECKS SW-REG AND RETURNS TO *+1 
*          IF OPTION BIT IS SET, OR TO *+2 IF 
*          NOT SET. B-REG MUST CONTAIN MASK OF
*          BIT TO BE CHECKED. 
      SPC 1 
CHKSI NOP 
      STA SAVA      SAVE A-REG
      LIA 1         INPUT SW-REG
      AND B         GET BIT OF INTEREST 
      SZA,RSS       IS IT ON? 
      ISZ CHKSI     NO. RETURN + 2
      LDA SAVA      YES. RETURN+1 
      JMP CHKSI,I 
      SPC 2 
B2ASC NOP           OCTAL ASCII 
      AND A77 
      LDB A 
      BRS,BRS 
      BRS 
      BLF,BLF 
      AND A7
      IOR B 
      IOR D60 
      JMP B2ASC,I 
      SPC 2 
DATAI NOP           CHANGE DATA IN A TO ASCII AND 
      STA DX          STORE IN LOCATION IN B
      STB DADD
      JSB B2ASC     CHANGE TWO LEAST SIG CH TO ASCII
      LDB DADD
      ADB A2        MODIFY ADDRESS
      STA B,I       STORE TWO CHARACTERS
      LDA DX
      ALF,ALF 
      RAL,RAL 
      JSB B2ASC     CHANGE NEXT TWO CH TO ASCII 
      LDB DADD
      INB           MODIFY ADDRESS
      STA B,I       STORE TWO CHARACTERS
      LDA DX
      AND P0
      ALF 
      JSB B2ASC     CHANGE TWO MOST SIG CH TO ASCII 
      STA DADD,I    STORE FINAL TWO CHARACTERS
      JMP DATAI,I 
* 
DX    BSS 1         DATA TO BE CONVERTED
DADD  BSS 1         ADDRESS WHERE ASCII CH MUST GO
      SPC 2 
* 
* THIS SR REPORTS ERRORS THROUGH THE TTY AND/OR THE T-REG.
*  DATA, IF ANY, IS DISPLAYED IN THE A&B REGISTERS. 
* 
ERRI  NOP 
      CLC 0,C 
      STA SAVA      SAVE
      STB SAVB       REGISTERS
* 
      CCB           SUBT 1 FROM RETURN ADDR TO GET
      ADB ERRI       ADDR OF E.XX IN B-REG
* 
      LDA FER       FIND POSITION OF E.XX IN ERROR
SERCH CPB A,I        ADDRESS TABLE
      JMP FND 
      INA 
      JMP SERCH 
FND   ADA FERC
      STA T.POS     STORE TABLE POSITION
* 
      JSB TTSK,I    USE TTY?
      LDA T.POS     YES. GET MSG ADDR FROM TABLE
      LDB FMI 
      JMP *+2 
      JMP CHT       NO
      ADB A 
      LDB B,I       MESSAGE ADDR IN B 
      ADA FML       GET MSG LENGTH FROM TABLE 
      LDA A,I       MESSAGE LENGTH IN A 
      JSB TTY.O,I   PRINT ERROR MESSAGE 
* 
CHT   LDB CHLT      GET CODED HALT FROM TABLE 
      ADB T.POS 
      LDB B,I 
      STB EXX       STORE CODED HALT AT EXX 
* 
      LDB BT14
      JSB CHKSW,I   ERROR HALTS SUPPRESSED? 
      JMP EXX+1     YES 
      LDA DAOUT     NO. PUT DATA IN A&B REGS
      LDB DAIN
EXX   HLT XX        CODED ERROR HALT
      LDA DAOUT 
      LDB DAIN
      JMP *+1,I     RETN *+1
      DEF ERRI,I
* 
      SKP 
* 
* THIS SR RETURNS TO *+1 IF TTY IS AVAILABLE AND NOT
*  SUPPRESSED, OTHERWISE TO *+4.
* 
TTSKI NOP 
      CLF 0         DISABLE INT SYS 
      LDB TTSKI 
      ADB A3        ADD 3 TO RETURN ADDR
      STB RETN4 
      LDA NTTY
      SZA           TTY AVAILABLE?
      JMP RETN4,I   NO, RETN *+4
      LDB BT11      YES 
      JSB CHKSW,I   TTY SUPPRESED?
      JMP RETN4,I   YES, RETN *+4 
      JMP TTSKI,I   NO, RETN *+1
* 
RETN4 NOP 
      SPC 2 
* 
* THIS SR REPORTS DMA1 FLAG ERRORS
* 
FLGI1 NOP 
      LDA DAOUT 
      STA TEMP
      LDA FLGI1     PUT RETN ADDR IN DAOUT. WILL BE 
      STA DAOUT      PUT IN A-REG DURING ERR ROUTINE
E50   JSB ERROR,I * DMA1 FLG NOT SET AFTER XFR
      LDA TEMP
      STA DAOUT 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      JMP FLGI1,I   RETN *+1
      SPC 2 
* 
* THIS SR REPORTS DMA2 FLAG ERRORS
* 
FLGI2 NOP 
      LDA DAOUT 
      STA TEMP
      LDA FLGI2     PUT RETN ADDR IN DAOUT. WILL BE 
      STA DAOUT      PUT IN A-REG DURING ERR ROUTINE
E53   JSB ERROR,I * DMA2 FLG NOT SET AFTER XFR
      LDA TEMP
      STA DAOUT 
      JSB H/L,I     CHECK FOR LOOP ON TEST
      JMP FLGI2,I   RETN *+1
* 
TEMP  NOP           TEMP STORAGE FOR DAOUT
      SPC 2 
* 
* SET UP DMA1 FOR OUTPUT. MEM ADDR IN A, COMPLEMENT WRD-CNT IN B
* 
OUT1I NOP 
      CLC 2         PREPARE TO RECV MEM ADDR
      OTA 2         OUTPUT MEM ADDR 
      STC 2         PREPARE TO RECV WRD-CNT 
      OTB 2         OUTPUT WRD CNT
      LDA K0        CTL-WRD=STC; WORD; CLC
      IOR CHA       INCLUDE I/O SELECT CODE 
      OTA 6         OUTPUT PROG CTL-WRD 
CH70  CLC CH
CH71  STF CH        GENERATE SRQ TO DMA1
      JMP OUT1I,I   RETN *+1
      SPC 2 
* 
* SET UP DMA2 FOR OUTPUT. SAME AS FOR DMA1 (OUT1I). 
* 
OUT2I NOP 
      CLC 3 
      OTA 3 
      STC 3 
      OTB 3 
      LDA K0
      IOR CHA 
      OTA 7 
CH72  CLC CH
CH73  STF CH
      JMP OUT2I,I 
      SPC 2 
* 
* SET UP DMA1 FOR INPUT. MEM ADDR IN A, COMPLEMENT WRD-CNT IN B 
* 
IN1I  NOP 
      IOR BT15      SET INPUT BIT IN MEM ADDR WORD
      JSB OUT1,I
      JMP IN1I,I    RETN *+1
      SPC 2 
* 
* SET UP DMA2 FOR INPUT. SAME AS FOR DMA1 (IN1I). 
* 
IN2I  NOP 
      IOR BT15
      JSB OUT2,I
      JMP IN2I,I
      SPC 3 
PWD3  DEF PWOU3 
DD1   DEF DOUT1 
DD2   DEF DOUT2 
T.20I DEF T.20
      HED DIAGNOSTIC MESSAGES 
      SUP 
M0    ASC 12,H0. START DMA DIAGNOSTIC 
L0    EQU *+*-M0-M0 
M1    ASC 10,E1. CLF6 OR SFS6 ERR 
L1    EQU *+*-M1-M1 
M2    ASC 10,E2. CLF6 OR SFC6 ERR 
L2    EQU *+*-M2-M2 
M3    ASC 10,E3. STF6 OR SFC6 ERR 
L3    EQU *+*-M3-M3 
M4    ASC 10,E4. STF6 OR SFS6 ERR 
L4    EQU *+*-M4-M4 
M5    ASC 10,E5. CLF7 OR SFS7 ERR 
L5    EQU *+*-M5-M5 
M6    ASC 10,E6. CLF7 OR SFC7 ERR 
L6    EQU *+*-M6-M6 
M7    ASC 10,E7. STF7 OR SFC7 ERR 
L7    EQU *+*-M7-M7 
M10   ASC 11,E10. STF7 OR SFS7 ERR
L10   EQU *+*-M10-M10 
M13   ASC 11,E13. STF0 OR SFC0 ERR
L13   EQU *+*-M13-M13 
M14   ASC 11,E14. STF0 OR SFS0 ERR
L14   EQU *+*-M14-M14 
M15   ASC 07,E15. NO D1 INT 
L15   EQU *+*-M15-M15 
M16   ASC 07,E16. NO D2 INT 
L16   EQU *+*-M16-M16 
M17   ASC 10,E17. D1 RTN ADDR ERR 
L17   EQU *+*-M17-M17 
M20   ASC 10,E20. D2 RTN ADDR ERR 
L20   EQU *+*-M20-M20 
M21   ASC 08,E21. D1 IAK ERR
L21   EQU *+*-M21-M21 
M22   ASC 08,E22. D2 IAK ERR
L22   EQU *+*-M22-M22 
M23   ASC 08,E23. D1 CLC0 ERR 
L23   EQU *+*-M23-M23 
M24   ASC 07,E24. CLC6 ERR
L24   EQU *+*-M24-M24 
M25   ASC 08,E25. D2 CLC0 ERR 
L25   EQU *+*-M25-M25 
M26   ASC 07,E26. CLC7 ERR
L26   EQU *+*-M26-M26 
M35   ASC 12,E35. D1-D2 PRIORITY ERR
L35   EQU *+*-M35-M35 
M36   ASC 12,E36. D2-IO PRIORITY ERR
L36   EQU *+*-M36-M36 
M37   ASC 12,E37. D1-IO PRIORITY ERR
L37   EQU *+*-M37-M37 
M40   ASC 06,E40. WC1 IS
M40A  ASC 09,XXXXXX, SHOULD BE
M40B  ASC 03,XXXXXX 
L40   EQU *+*-M40-M40 
M41   ASC 06,E41. WC2 IS
M41A  ASC 09,XXXXXX, SHOULD BE
M41B  ASC 03,XXXXXX 
L41   EQU *+*-M41-M41 
M42   ASC 07,E42. NO D1 INT 
L42   EQU *+*-M42-M42 
M43   ASC 07,E43. NO D2 INT 
L43   EQU *+*-M43-M43 
M44   ASC 06,E44. WC1 IS
M44A  ASC 11,XXXXXX, SHOULD BE ZERO 
L44   EQU *+*-M44-M44 
M45   ASC 09,E45. D1 INT LOC =
M45A  ASC 09,XXXXXX, SHOULD BE
M45B  ASC 03,XXXXXX 
L45   EQU *+*-M45-M45 
M46   ASC 06,E46. WC2 IS
M46A  ASC 11,XXXXXX, SHOULD BE ZERO 
L46   EQU *+*-M46-M46 
M47   ASC 09,E47. D2 INT LOC =
M47A  ASC 09,XXXXXX, SHOULD BE
M47B  ASC 03,XXXXXX 
L47   EQU *+*-M47-M47 
M50   ASC 08,E50. D1 FLG CLR
L50   EQU *+*-M50-M50 
M51   ASC 06,E51. D1 OUT= 
M51A  ASC 06,XXXXXX, IN=
M51B  ASC 07,XXXXXX, ADDR=
M51C  ASC 03,XXXXXX 
L51   EQU *+*-M51-M51 
M53   ASC 08,E53. D2 FLG CLR
L53   EQU *+*-M53-M53 
M54   ASC 06,E54. D2 OUT= 
M54A  ASC 06,XXXXXX, IN=
M54B  ASC 07,XXXXXX, ADDR=
M54C  ASC 03,XXXXXX 
L54   EQU *+*-M54-M54 
M56   ASC 10,E56. D1 CTL WRD ERR
L56   EQU *+*-M56-M56 
M57   ASC 10,E57. D1 CTL WRD ERR
L57   EQU *+*-M57-M57 
M60   ASC 10,E60. D2 CTL WRD ERR
L60   EQU *+*-M60-M60 
M61   ASC 10,E61. D2 CTL WRD ERR
L61   EQU *+*-M61-M61 
M62   ASC 10,E62. D1 CTL WRD ERR
L62   EQU *+*-M62-M62 
M63   ASC 10,E63. D1 CTL WRD ERR
L63   EQU *+*-M63-M63 
M64   ASC 10,E64. D2 CTL WRD ERR
L64   EQU *+*-M64-M64 
M65   ASC 10,E65. D2 CTL WRD ERR
L65   EQU *+*-M65-M65 
M67   ASC 09,E67. D1 OUT. GOOD= 
M67A  ASC 06,XXXXXX, BAD= 
M67B  ASC 03,XXXXXX 
L67   EQU *+*-M67-M67 
M71   ASC 09,E71. D2 OUT. GOOD= 
M71A  ASC 06,XXXXXX, BAD= 
M71B  ASC 03,XXXXXX 
L71   EQU *+*-M71-M71 
M73   ASC 09,E137. D1 IN. GOOD= 
M73A  ASC 06,XXXXXX, BAD= 
M73B  ASC 03,XXXXXX 
L73   EQU *+*-M73-M73 
M74   ASC 10,E136. D1-I/O FLG SET 
L74   EQU *+*-M74-M74 
M75   ASC 09,E75. D1 OUT. GOOD= 
M75A  ASC 06,XXXXXX, BAD= 
M75B  ASC 03,XXXXXX 
L75   EQU *+*-M75-M75 
M76   ASC 09,E76. D1 OUT. GOOD= 
M76A  ASC 06,XXXXXX, BAD= 
M76B  ASC 03,XXXXXX 
L76   EQU *+*-M76-M76 
M77   ASC 10,H77. END DIAGNOSTIC
L77   EQU *+*-M77-M77 
M100  ASC 08,E100. D1 IAK ERR 
L100  EQU *+*-M100-M100 
M101  ASC 10,E101. D2 OUT. GOOD=
M101A ASC 06,XXXXXX, BAD= 
M101B ASC 03,XXXXXX 
L101  EQU *+*-M101-M101 
M102  ASC 10,E102. D2 OUT. GOOD=
M102A ASC 06,XXXXXX, BAD= 
M102B ASC 03,XXXXXX 
L102  EQU *+*-M102-M102 
M103  ASC 08,E103. D2 IAK ERR 
L103  EQU *+*-M103-M103 
M104  ASC 09,E104. D1 IN. GOOD= 
M104A ASC 06,XXXXXX, BAD= 
M104B ASC 03,XXXXXX 
L104  EQU *+*-M104-M104 
M105  ASC 13,E105. PRIORITY OR PH5 ERR
L105  EQU *+*-M105-M105 
M106  ASC 09,E106. D2 IN. GOOD= 
M106A ASC 06,XXXXXX, BAD= 
M106B ASC 03,XXXXXX 
L106  EQU *+*-M106-M106 
M112  ASC 11,E112. D2--I/O FLG SET
L112  EQU *+*-M112-M112 
M115  ASC 09,E115. D2 IN. GOOD= 
M115A ASC 06,XXXXXX, BAD= 
M115B ASC 03,XXXXXX 
L115  EQU *+*-M115-M115 
M116  ASC 09,E116. D1 CLF0 ERR
L116  EQU *+*-M116-M116 
M117  ASC 09,E117. D2 CLF0 ERR
L117  EQU *+*-M117-M117 
M121  ASC 08,E121. D1 SC ERR
L121  EQU *+*-M121-M121 
M122  ASC 08,E122. D1 SC ERR
L122  EQU *+*-M122-M122 
M123  ASC 08,E123. D2 SC ERR
L123  EQU *+*-M123-M123 
M124  ASC 08,E124. D2 SC ERR
L124  EQU *+*-M124-M124 
M125  ASC 08,E125. D1 SC ERR
L125  EQU *+*-M125-M125 
M126  ASC 08,E126. D1 SC ERR
L126  EQU *+*-M126-M126 
M127  ASC 08,E127. D2 SC ERR
L127  EQU *+*-M127-M127 
M130  ASC 08,E130. D2 SC ERR
L130  EQU *+*-M130-M130 
M131  ASC 08,E131. D1 CRS ERR 
L131  EQU *+*-M131-M131 
M132  ASC 08,E132. D2 CRS ERR 
L132  EQU *+*-M132-M132 
M133  ASC 07,E133. STF6 ERR 
L133  EQU *+*-M133-M133 
M134  ASC 07,E134. STF7 ERR 
L134  EQU *+*-M134-M134 
M135  ASC 08,E135. NO I/O INT 
L135  EQU *+*-M135-M135 
FWAM  EQU *         FIRST WORD AVAILABLE MEMORY 
      BSS 63
OUT   OCT 0 
VLAST EQU * 
      END 
                                                                                                            