ASMB,A,B,L ****HP 1000 L/XL-SERIES KERNEL DIAGNOSTIC **** * * * ***************************************************************** * * (C) COPYRIGHT HEWLETT-PACKARD COMPANY 1980. ALL RIGHTS * * * RESERVED. NO PART OF THIS PROGRAM MAY BE PHOTOCOPIED, * * * REPRODUCED OR TRANSLATED INTO ANOTHER PROGRAM LANGUAGE WITHOUT* * * THE PRIOR WRITTEN CONSENT OF HEWLETT-PACKARD COMPANY. * * ***************************************************************** * * NAME: L/XL KERNEL DIAGNOSTIC * SOURCE: 24397-18002 DATE CODE 2040 * ABS: 24397-16002 * PGMR: D.L.M.,D.W.N.,M.T.W. * ORG 0B OCT 0 OCT 20000 * * * **THE 1000 L/XL-SERIES GENERAL DIAGNOSTIC** * * * * THE KERNEL DIAGNOSTIC IS A STAND-ALONE PROGRAM THAT * IS USED TO VERIFY THE OPERATION OF THE L-SERIES COMPUTER. * THE PROGRAM TESTS MEMORY, CPU INSTRUCTIONS, PROCESSOR * FUNCTIONS, ALL I/O INSTRUCTION EXECUTION, * 95% OF THE I/O CHIP LOGIC, THE CPU I/O FUNCTIONS, * THE INTERRUPT SYSTEM, OVERFLOW AND OVERFLOW INTERRUPTS, * THE TIME BASE GENERATOR, UNIMPLEMENTED INSTRUCTION * TRAP, MEMORY PROTECT, AND DMA. IT INCLUDES A MULTIPLE * DMA TRANSFER TEST WHICH INVOLVES ALL I/O CHIPS IN * THE SYSTEM SIMULTANEOUSLY CONTENDING FOR SERVICE AND * INTERRUPT PRIORITY. THE I/O FUNCTIONS NOT TESTED * BY THIS DIAGNOSTIC ARE THOSE DEALING DIRECTLY WITH * THE LOGIC ON SPECIFIC INTERFACE CARDS. THOSE FUNCTIONS * WILL BE DEALT WITH IN THE INTERFACE DIAGNOSTICS AND * WILL BE DOCUMENTED IN THE ERS. * * *ERROR REPORTING * THIS DIAGNOSTIC REPORTS ERRORS IN TWO FORMATS. THE * FIRST IS USED WHENEVER A VIRTUAL CONTROL PANEL (VCP) * IS CONFIGURED IN THE SYSTEM AND MAKES USE OF THE VCP * CODE CONTAINED IN THE CPU PRETEST/BOOT ROMS. IF AN * ERROR OCCURS AND THE PRESENCE OF AN RFP IS DETECTED, SKP * * THE STATUS CODES ARE AS FOLLOWS: * * STATUS - MEANING * * 10 CPU FAILURE * 11 PROCESSOR FUNCTIONS UNDER TEST * 12 MEMORY PROBABLY FAILED * 13 FAILURE IN I/O SYSTEM * 14 ILLEGAL INTERRUPT OCCURRED * 11 MEMORY PROTECT ON, PROCESSOR HUNG UP * (FLASHING IF BREAK IS HELD OFF) * 20-77 SELECT CODE OF CHIP UNDER TEST * * *KEY REFERENCES * THE FOLLOWING LABELS ARE USED FREQUENTLY THROUGHOUT * THE DIAGNOSTIC AND ARE LISTED HERE FOR REFERENCE: * * LABEL - MEANING * * S/C SELECT CODE * LEDS CPU STATUS LEDS ON PROCESSOR * GR GLOBAL REGISTER * RFP REMOTE FRONT PANEL * CIR CENTRAL INTERRUPT REGISTER * PE PARITY ERROR * MPT MEMORY PROTECT * VIOLA MEMORY PROTECT VIOLATION REGISTER * FENCE MEMORY PROTECT FENCE * TBG TIME BASE GENERATOR * INMSK INTERRUPT MASK REGISTER * CONAD DMA CONFIGURATION ADDRESS REGISTER * DMAAD DMA ADDRESS REGISTER * WRDCT DMA WORD COUNT REGISTER * CWRD1 DMA CONTROL WORD 1 REGISTER * M2 I/O CHIP M2 REGISTER * N1 I/O CHIP N1 REGISTER * N2 I/O CHIP N2 REGISTER * DF0 I/O CHIP DMA S/C 20 * DF1 I/O CHIP DMA S/C 21 * DF2 I/O CHIP DMA S/C 22 * DF3 I/O CHIP DMA S/C 23 * GSC REFERENCES DEVICE FLAG OR CONTROL SELECT CODE 30 * TRPXX TRAP CELL CORRESPONDING TO SELECT CODE XX * SKP * * THE STARTING ADDRESS FOR THE DIAGNOSTIC IS ADDRESS 4. * * *TRAP CELLS * ORG 2 TRP02 JMP *+1,I BOOT-UP STARTING POINT TRP03 DEF START STARTING ADDRESS OF KERNEL TRP04 NOP POWER-FAIL AUTO RESTART INT. TRP05 JSB ILI,I PARITY ERROR INTERRUPT TRP06 JSB ILI,I TIME BASE GENERATOR INTERRUPT TRP07 JSB ILI,I MEMORY PROTECT INTERRUPT TRP10 JSB ILI,I UNIMPLEMENTED INSTRUCTION INTERRUPT ILI DEF ILINT ILLEGAL INTERRUPT POINTER TRP12 JSB ILI,I ILLEGAL INTERRUPT TRP13 JSB ILI,I ILLEGAL INTERRUPT TRP14 JSB ILI,I ILLEGAL INTERRUPT TRP15 JSB ILI,I ILLEGAL INTERRUPT TRP16 JSB ILI,I ILLEGAL INTERRUPT TRP17 JSB ILI,I ILLEGAL INTERRUPT TRP20 JSB ILI,I ILLEGAL INTERRUPT TRP21 JSB ILI,I ILLEGAL INTERRUPT TRP22 JSB ILI,I ILLEGAL INTERRUPT TRP23 JSB ILI,I ILLEGAL INTERRUPT TRP24 JSB ILI,I ILLEGAL INTERRUPT TRP25 JSB ILI,I ILLEGAL INTERRUPT TRP26 JSB ILI,I ILLEGAL INTERRUPT TRP27 JSB ILI,I ILLEGAL INTERRUPT TRP30 JSB ILI,I ILLEGAL INTERRUPT TRP31 JSB ILI,I ILLEGAL INTERRUPT TRP32 JSB ILI,I ILLEGAL INTERRUPT TRP33 JSB ILI,I ILLEGAL INTERRUPT TRP34 JSB ILI,I ILLEGAL INTERRUPT TRP35 JSB ILI,I ILLEGAL INTERRUPT TRP36 JSB ILI,I ILLEGAL INTERRUPT TRP37 JSB ILI,I ILLEGAL INTERRUPT TRP40 JSB ILI,I ILLEGAL INTERRUPT TRP41 JSB ILI,I ILLEGAL INTERRUPT TRP42 JSB ILI,I ILLEGAL INTERRUPT TRP43 JSB ILI,I ILLEGAL INTERRUPT TRP44 JSB ILI,I ILLEGAL INTERRUPT TRP45 JSB ILI,I ILLEGAL INTERRUPT TRP46 JSB ILI,I ILLEGAL INTERRUPT TRP47 JSB ILI,I ILLEGAL INTERRUPT TRP50 JSB ILI,I ILLEGAL INTERRUPT TRP51 JSB ILI,I ILLEGAL INTERRUPT TRP52 JSB ILI,I ILLEGAL INTERRUPT TRP53 JSB ILI,I ILLEGAL INTERRUPT TRP54 JSB ILI,I ILLEGAL INTERRUPT TRP55 JSB ILI,I ILLEGAL INTERRUPT SKP TRP56 JSB ILI,I ILLEGAL INTERRUPT TRP57 JSB ILI,I ILLEGAL INTERRUPT TRP60 JSB ILI,I ILLEGAL INTERRUPT TRP61 JSB ILI,I ILLEGAL INTERRUPT TRP62 JSB ILI,I ILLEGAL INTERRUPT TRP63 JSB ILI,I ILLEGAL INTERRUPT TRP64 JSB ILI,I ILLEGAL INTERRUPT TRP65 JSB ILI,I ILLEGAL INTERRUPT TRP66 JSB ILI,I ILLEGAL INTERRUPT TRP67 JSB ILI,I ILLEGAL INTERRUPT TRP70 JSB ILI,I ILLEGAL INTERRUPT TRP71 JSB ILI,I ILLEGAL INTERRUPT TRP72 JSB ILI,I ILLEGAL INTERRUPT TRP73 JSB ILI,I ILLEGAL INTERRUPT TRP74 JSB ILI,I ILLEGAL INTERRUPT TRP75 JSB ILI,I ILLEGAL INTERRUPT TRP76 JSB ILI,I ILLEGAL INTERRUPT TRP77 JSB ILI,I ILLEGAL INTERRUPT SPC 3 * THESE LOCATIONS ARE USED FOR MEMORY PROTECT TESTS * NOP NOP SKP * * *SUBROUTINES TO FORM JMP AND JSB TARGETS * FOR INTERRUPT ROUTINES. ASSUMES A CONTAINS * TRAP CELL ADDRESS ENTERING ROUTINE. * JPTRP NOP RESERVED FOR ADDRESS OF IN-LINE DEF STB SAVEM SAVE B LDB JADII STB A,I TRAP CELL = JMP ADINT,I LDB JPTRP,I STB ADINT ADINT = INTERRUPT RETURN ADDRESS STA SAVSC SAVSC = TRAP CELL ADDRESS ISZ JPTRP POINTS TO IN-LINE RETURN ADDRESS LDB SAVEM RESTORE B JMP JPTRP,I RETURN TO PROGRAM * * JADII JMP ADINT,I ADINT NOP SAVSC NOP * * RSTRP NOP RETURN ADDRESS FROM PROGRAM STA SAVEM SAVE A LDA JSBIL GET JSB ILINT FOR TRAP CELL STA SAVSC,I RESTORE TRAP CELL LDA SAVEM RESTORE A JMP RSTRP,I RETURN TO PROGRAM * * JSTRP NOP RESERVED FOR ADDRESS OF IN-LINE DEF STB SAVEM SAVE B LDB JSAII STB A,I TRAP CELL = JSB JSADI,I LDB JSTRP,I STB JSADI JSADI = INTERRUPT RETURN ADDRESS STA SAVSC SAVSC = TRAP CELL ADDRESS ISZ JSTRP POINTS TO IN-LINE RETURN ADDRESS LDB SAVEM RESTORE B JMP JSTRP,I RETURN TO PROGRAM * * JSAII JSB JSADI,I JSADI NOP SKP * * **CHKIN** CHECKS MEMORY PROTECT INTERRUPT * INFORMATION TO DETERMINE IF THE VIOLATION * REGISTER CONTENTS ARE CORRECT. * CHKIN NOP CLF 0 TURN OFF INTERRUPT SYSTEM. STA SAVA SAVE A AND B REG STB SAVA+1 LDA EXPVR GET EXPECTED VIOLATION REG. LIB VIOLA,C GET ACTUAL VIOLATION REGISTER. CPB A ACTUAL VR = EXPECTED VR? RSS CHKER JSB PROER,I NO CHKRN LDA SPTST GET SPECIAL TEST INDICATOR. SZA IS THIS A SPECIAL TEST? JMP INCRT YES! GO UPDATE RETURN. ISZ CHKIN NO. INC CHKIN PAST HLT 03. JMP NOINC GO RETURN INCRT LDA B,I GET VIOLATING INSTRUCTION CPA VILST IS IT A JSB 100B? RSS YES JMP RETMO NO - CONTINUE LDB CHKIN GET JSB TARGET+1 FROM CHKIN CPB B101 WAS ILLEGAL JSB PROCESSED CORRECTLY? RSS YES JSB CPUER,I NO RETMO LDA MOVAD SET RETURN ADDRESS TO MOVLT STA CHKIN NOINC LDA SAVA RESTORE A AND B REGISTERS. LDB SAVA+1 JMP CHKIN,I RETURN TO TESTING. * * * * * **INTMP** INITIALIZES MEMORY PROTECT BY * LOADING THE FENCE REGISTER. * THE B REGISTER MUST CONTAIN THE ADDRESS TO * BE LOADED IN THE FENCE REGISTER. * * * INTMP NOP OTB FENCE OUTPUT TO FENCE REGISTER. STB FENVA SAVE ACTUAL FENCE VALUE. STF 0 TURN ON INTERRUPT SYSTEM. JMP INTMP,I RETURN TO TEST. HED TEST PARAMETERS * *CONSTANTS AND PARAMETERS * MEMPR DEF MPTST MOD.2 DEF MOD.1 SCTAD DEF SCTBL .5RTN DEF INT.5-1 B1ADR DEF B1 CONF1 DEF DMP01 CONF2 DEF DMP02 CONF3 DEF DMP03 CONF4 DEF DMP04 CONFX DEF DMPX CONFY DEF DMPY CONMD DEF MDM00 STBAD DEF STBAI IOVAD DEF IOVIO ALLAD DEF ALLIN ATBAD DEF ALLTB LECOD DEF LENCD EA001 DEF TH001 EA002 DEF TH002 EXA01 DEF THT10 MP08D DEF MPT08 EA003 DEF TH003 CHEAD DEF CHKRN IPNTR DEF VILST NTSAD DEF TST07 BCLAD DEF BUFCL LINAD DEF INLIN DMTAD DEF DMMPT STPAD DEF STPDM MOVAD DEF MOVLT M08AD DEF MPT08 RLOP DEF RLOOP CLFAD DEF CLF0 .IOTS DEF TST05 IOER DEF IOERR CPUER DEF CPERR PROER DEF PRERR DISP DEF DSPLY HALTP DEF HALT DISP5 DEF DSPL1 .END OCT 20000 SKP BIOIS STF GSC INSTRUCION FOR I/O PARITY TEST BDN1 DEF BADIN MDSC DEF MODSC HLT03 HLT 03 CFTBG CLF TBG LIASC LIA 00 MIBSC MIB 00,C LIVIO LIA VIOLA,C LISCC LIA 00,C SSC DEF SETSC LIA24 LIA M2 INSTRUCTION IORTN JMP IORT0,I RETURN INSTRUCTION IORT0 DEF IORT1 TO CURRENT PAGE CLC0 DEF CLC0R * * *JSB'S AND JMP'S * JSBIL JSB ILI,I RTNJS JSB CHKIN DMMTR JMP DMTAD,I JARTN JMP A,I JBRTN JMP B,I * * *CONFIGURATION DATA FOR DMA * DMP01 OCT 000200 IN OCT 001000 DMAAD = 1000 OCT 177777 WORD COUNT = -1 DMP02 OCT 105200 CONT,CINT,FOUR,IN OCT 000000 CWRD2 = 0 OCT 001004 DMAAD = 1004 OCT 177777 WORD COUNT = -1 DMP03 OCT 114400 CONT,CINT,AUTO,RES OCT 001000 DMAAD = 1000 OCT 177777 WORD COUNT = -1 OCT 005400 CINT,FOUR,AUTO OCT 000000 CWRD2 = 0 OCT 101005 DMAAD = 1005 OCT 177777 WORD COUNT = -1 DMP04 OCT 014400 RES,CINT,AUTO OCT 001006 DMAAD = 1006 OCT 177777 WORD COUNT = -1 DMPX OCT 000200 IN OCT 001010 DMAAD = 1010 OCT 177300 WORD COUNT = -500B DMPY NOP DMPZ OCT 000200 IN OCT 020000 DMAAD = CONAD = 20000 OCT 120001 WORD COUNT = -57777B SKP * * *CONFIGURATION DATA FOR THE MULTI-CHIP DMA TEST * MDMCW OCT 000200 IN MDMWD OCT 177770 WORD COUNT = -10B * * *DMA ADDRESS REGISTER/CONFIG ADDRESS REGISTER VALUES * MDM00 OCT 1000 MDM01 OCT 1010 MDM02 OCT 1020 MDM03 OCT 1030 MDM04 OCT 1040 MDM05 OCT 1050 MDM06 OCT 1060 MDM07 OCT 1070 MDM10 OCT 1100 MDM11 OCT 1110 MDM12 OCT 1120 MDM13 OCT 1130 MDM14 OCT 1140 MDM15 OCT 1150 MDM16 OCT 1160 MDM17 OCT 1170 MDM20 OCT 1200 MDM21 OCT 1210 MDM22 OCT 1220 MDM23 OCT 1230 MDM24 OCT 1240 MDM25 OCT 1250 MDM26 OCT 1260 MDM27 OCT 1270 MDM30 OCT 1300 MDM31 OCT 1310 MDM32 OCT 1320 MDM33 OCT 1330 MDM34 OCT 1340 MDM35 OCT 1350 MDM36 OCT 1360 MDM37 OCT 1370 * * (CONTINUED) * SKP MDM40 OCT 1400 MDM41 OCT 1410 MDM42 OCT 1420 MDM43 OCT 1430 MDM44 OCT 1440 MDM45 OCT 1450 MDM46 OCT 1460 MDM47 OCT 1470 MDM50 OCT 1500 MDM51 OCT 1510 MDM52 OCT 1520 MDM53 OCT 1530 MDM54 OCT 1540 MDM55 OCT 1550 MDM56 OCT 1560 MDM57 OCT 1570 MDM60 OCT 1600 MDM61 OCT 1610 * SKP * POINT NOP SELECT CODE TABLE POINTER * * *SELECT CODE TABLE * SCTBL NOP FILL2 REP 60B NOP SKP * *TEMPORARY STORAGE LOCATIONS * ERRA NOP TEMP. STORAGE REG. FOR A & B ERRB NOP FOR ERROR ROUTINES IN KERNAL ERRS NOP TEMP. STORAGE REG. FOR ERROR ROUTINE. TEMP0 NOP TEMP1 NOP TEMP2 NOP TEMP3 NOP TEMP4 NOP TEMP5 NOP TEMP6 NOP TEMP7 NOP TEMP8 NOP TEMP9 NOP TMP0 NOP TMP1 NOP SAVEM NOP SAVEA NOP SAVED NOP MCNTR NOP EXPVR NOP INPNT NOP BUFPT NOP FENVA NOP SAVA NOP NOP SPTST NOP FENP1 NOP EOM NOP END OF MEMORY ADDRESS CNTR NOP ERROR COUNTER SKP * * *EQUATES * A EQU 0 B EQU 1 SC EQU 20B LEDS EQU 01 GR EQU 02 RFP EQU 03 CIR EQU 04 PES EQU 05 PETRP EQU 05 MPT EQU 07 MTRAP EQU 07 VIOLA EQU 07 FENCE EQU 07 TBG EQU 06 INMSK EQU 00 CONAD EQU 20B DF0 EQU 20B CWRD1 EQU 21B DF1 EQU 21B DMAAD EQU 22B DF2 EQU 22B WRDCT EQU 23B DF3 EQU 23B DF4 EQU 24B M2 EQU 24B N1 EQU 25B N2 EQU 26B GSC EQU 30B DR EQU 30B CTL EQU 31B SKP * *CONSTANTS * BMPT OCT 7 B1 OCT 1 B2 OCT 2 B3 OCT 3 B4 OCT 4 B5 OCT 5 B6 OCT 6 B7 OCT 7 B10 OCT 10 B11 OCT 11 B12 OCT 12 B13 OCT 13 B14 OCT 14 B15 OCT 15 B16 OCT 16 B17 OCT 17 B20 OCT 20 B26 OCT 26 B40 OCT 40 B52 OCT 52 B60 OCT 60 B70 OCT 70 B77 OCT 77 B100 OCT 100 B101 OCT 101 B140 OCT 140 B177 OCT 177 B200 OCT 200 MB260 OCT 177520 = -260B B1000 OCT 1000 B1400 OCT 1400 B1510 OCT 1510 B1511 OCT 1511 B1560 OCT 1560 B1777 OCT 1777 B2000 OCT 2000 B3000 OCT 3000 B11MS OCT 1722 MB9MS OCT 177330 SCM OCT 100077 * SKP * * *BIT PATTERNS * PAT00 OCT 177700 PAT01 OCT 177716 PAT02 OCT 125252 PAT03 OCT 165653 PAT04 OCT 040401 PAT05 OCT 070000 PAT06 OCT 000401 BINARY 0000000100000001 PAT07 OCT 007700 PAT10 OCT 100000 PAT11 OCT 000016 PAT12 OCT 000006 PAT13 OCT 177706 PAT14 OCT 177776 PAT15 OCT 077777 PAT16 OCT 007700 PAT17 OCT 004000 PAT20 OCT 004200 PAT21 OCT 004000 PAT22 OCT 000004 BINARY 0000000000000100 PAT23 OCT 167700 PAT24 OCT 103600 PAT25 OCT 017777 PAT26 OCT 100070 PAT27 OCT 005300 PAT30 OCT 000200 PAT31 OCT 020000 PAT32 OCT 163700 PAT33 OCT 172000 PAT34 OCT 102000 SKP * * *VIOLATING INSTRUCTION LIST * VILST JSB 100B ISZ 100B JMP 100B OCT 100600 JLA 100B OCT 104600 JLB 100B STA 100B STB 100B OCT 104400 DST CLC 0 CLF 6 LIA 7,C LIB 7,C MIA 7,C MIB 7,C OTA 7 OTB 7 SFC 6 SFS 6 STC 6 STF 6 HLT 03 CLC 0,C MIN1 DEC -1 END OF LIST SKP SKP .JP CPA BAS4P RSS JSB CPUER,I A MODIFIED BY JMP TO BASE PAGE CPB BPTEN RSS JSB CPUER,I B MODIFIED BY JMP TO BASE PAGE SOC JSB CPUER,I OV WAS INCORRECTLY SET SEZ,RSS JSB CPUER,I E WAS INCORRECTLY CLEARED * RETURN TO AFTER JMP TO BASE PAGE JMP .PG04,I * BPTEN OCT 000012 .PG04 DEF TST03 * * UNIMPLEMENTED INSTRUCTION PROCESSING ROUTINE * UIINT NOP RETURN ADDRESS ISZ TEMP7 INCREMENT TEMP7 JMP UIINT,I RETURN TO PROGRAM JSB PROER,I SPC 2 * BASE PAGE VALUES,LINKS AND STORAGE LOCATIONS BASEP OCT 077777 BAS1P OCT 052524 BAS2P OCT 077776 BAS3P OCT 052525 BAS4P NOP BAS5P OCT 1 DM2 DEC -2 DM5 DEC -5 SKP * PROCESSOR AND I/O REGISTER CHECK ROUTINES * IREGC NOP CLC PES TURN OFF THE PARITY SYSTEM LDA PAT02 GET A TEST PATTERN IR1 OTA CIR SEND TO CIR OTA PES AND TO PARITY REGISTER OTA FENCE,C AND TO MP VIOLATION REGISTER LDB B4 PUT A 4 IN B STA TEMP0 SAVE PATTERN TEMPORARILY AND B77 JSB IRGC1 CHECK OT*, LI*, MI* JSB PROER,I OT*, MI*, LI* FAILED OR REGISTER BAD LDA TEMP0 ELA,CLE,ERA STRIP OFF MSB LDB B5 CHECK PARITY REGISTER JSB IRGC1 CHECK OT*, MI*, LI* JSB PROER,I OT*, MI*, LI* BAD OR REGISTER FAILED LDB B7 CHECK OT*, MI*, LI* 7 JSB IRGC1 GO TO IT JSB PROER,I REGISTER OR ABOVE INSTRUCTIONS BAD SLA HAVE ALL PATTERNS BEEN CHECKED? JMP *+4 YES CMA NO - COMPLEMENT PATTERN STA TEMP0 SAVE IT JMP IR1 DO IT AGAIN STC PES TURN PARITY SYSTEM BACK ON JMP IREGC,I RETURN TO PROGRAM * * IRGC1 NOP ELA,CLE,ERA ADB MIBSC CREATE INSTR. MIB SC STB *+2 STORE IT IN-LINE CLB CLEAR B NOP RESERVED FOR INSTRUCTION CPA B ARE THEY THE SAME? RSS YES JMP IRGC1,I NO RETURN AND INDICATE ERROR LDB *-4 GET MERGE INSTRUCTION ADB B100 ADD 100B TO CREATE LIB INSTRUCTION STB *+2 CLB CLEAR B NOP RESERVED FOR INSTRUCTION CPA B ARE THEY THE SAME? ISZ IRGC1 YES - INCREMENT RETURN JMP IRGC1,I NO - RETURN SKP * * *MEMORY LOCATIONS 1000 - 1777 ARE RESERVED AS A * TRANSFER BUFFER FOR THE DMA TESTS HED MEMORY TEST * SAVE AND RESTORE A AND B REGISTERS ON START UP * ORG 2000B START LDB RSRIN PUT START INSTRUCTION STB TRP02 STB TRP04 IN POWER-FAIL TRAP SFS 4B CHECK FOR POWER GOING DOWN JMP PFWDN IT IS SZA IS THIS A AUTO RESTART JMP STRT0 NO LDA PFWC YES - WAS THERE A POWER DOWN? SZA,RSS ?? JMP PFWER NO THEN ERROR LDA AFLG YES - RESTOR FLAGS OTA 3 CORRECT DEVICE SSA AUTO OR MANUAL JMP STRT1 MANUAL OTA 2,C AUTO SO RESET FILE NUMBER LDB AFLG+1 OTB 25B JMP STRT1 * STRT0 STA AFLG OTA 2,C GET FILE NUMBER LIA 25B STA AFLG+1 * STRT1 CLC 0,C LDA RSTRF CHECK IF A RESTORE IS NECESSARY SZA,RSS IS IT? JMP *+5 NO SO CONTINUE JSB RSTR YES SO RESTORE AND STA RSTFD,I CLEAR RSTRF JMP *+1,I RESTART DEF *+1 SKP * PERFORM CHECKSUM ON FIRST TEST AREA * STA BADIN CLEAR AREAS WITH STA BAD2,I BAD PARITY STA BAD3,I STA BAD4,I STA SAVE CLEAR ALL STA RSTR SUBROUTINE RETURNS STA MERR STA MTSTR STA PTGN1 STA PTGNC STA ILINT STA DSPLY LDB CKSA STARTING ADDRESS OF CHECKSUM AREA ADA B,I BUILD CHECKSUM INB CPB CKEA END OF AREA? JMP *+2 YES JMP *-4 NO DO NEXT LOCATION SZA WAS THE MEMORY GOOD? JMP * NO - THEN DON'T TRY ANYTHING * LDA Z12 INDICATE IN MEMORY TEST OTA LEDS CLB CLEAR B LDA PFWC GET THE POWER FAIL TIMER STB PFWC RESET TIMER SZA,RSS WAS POWER GOING DOWN? JMP MEMTS NO SO STARRT MEMORY TEST ADA PFWCC YES. WAS POWER AVAILABLE LONG ENOUGH? SSA,RSS JMP MEMTS YES SO START MEMORY TEST PFWER LDA Z4 NO SO INDICATE POWER STA CNTR FAIL ERROR IN COUNTER JSB PROER,I GO DISPLAY IT SKP MEMTS LDA ZBFA SET FIRST BUFFER AREA STA FADD FIRST ADDRESS TO BE CHECKED ADA Z1777 MAKE LAST ADDRESS STA LADD AND SAVE IT JSB MTSTR GO DO TEST ON BUFFER AREA LDA Z2000 SET STARTING ADDRESS OF TEST AREA JSB SAVE SAVE THE AREA FIRST STA RSTFD+1,I LDA ZBFA GET RESTART DEF STA TRP03 AND PUT IN LOCATION 3 LDA DILN1 GET NEW ILL. INT. LOCATION STA ILI AND STORE IN 11 LDA ZBFA NOW GO TO NEW PAGE IOR *+2 JMP A,I DEF *+1-2000B EXECUTE OUT OF BASE PAGE JSB MTSTR DO TEST JSB RSTR RESTORE PROGRAM JMP *+1,I RETURN TO CURRENT PAGE DEF *+1 LDA Z12 NOW CHECK BASE PAGE FROM 12 UP JSB SAVE JSB MTSTR JSB RSTR LDA Z4000 MOVE THROUGH REST OF MEMORY JSB SAVE JSB MTSTR JSB RSTR LDA LADD INCREMENT TO NEXT ADDRESS CPA PLAD LAST PROGRAM ADDRESS JMP *+3 INA JMP *-7 NO DO THE PAGE LDB ZMXAD GET MEMORY MAX ADDRESS LDA ALT0 USE A PATTERN STA B,I STORE IT CPA B,I DID IT STORE? JMP MEMTO YES LDA B,I CHECK IF MEMORY WAS NOT REALLY THERE CMA,SZA,RSS ?? LDB ZMXAD+1 SORRY BUT IT WAS THERE MEMTO STB EOM SAVE MEMORY SIZE LDA PLAD NOW REST OF MEMORY INA STA FADD LDA EOM END OF MEMORY STA LADD JSB MTSTR RUN TEST JMP PEIT RUN PARITY ERROR INT. CHK. SKP * THESE ROUTINES ARE TO SAVE AND RESTORE THE * PROGRAM AREA THAT IS CURRENT UNDER TEST * THE ROUTINE IS ENTERED WITH A = TO STARTING ADDRESS * SAVE NOP STA FADD IOR Z1777 STA LADD LDA ZBFA STA RSTR LDB FADD SAVEL LDA B,I STA RSTR,I CPB LADD JMP *+4 INB ISZ RSTR JMP SAVEL CCA SET RESTORE FLAG STA RSTRF JMP SAVE,I NOW RETURN * RSTR NOP LDA ZBFA STA SAVE LDB FADD RSTRL LDA SAVE,I STA B,I CPB LADD JMP *+4 INB ISZ SAVE JMP RSTRL LDA Z2000 RESTORE NORMAL RESTART STA TRP03 LDA DILN0 RESTORE NORMAL ILL. INT. STA ILI CLA CLEAR RESTORE FLAG STA RSTRF JMP RSTR,I NOW RETURN * PFWDN CLC 4B DISABLE FURTHER POWER FAIL INTERRUPTS SFC 4B IS POWER GOING DOWN? JMP *+4 NO SO RESTART ISZ PFWC START TIMER NOP DELAY JMP *-4 STAY HERE CLA POWER BACK UP SO CLEAR TIMER STA PFWC LDA AFLG RESTORE A REGISTER RSRIN JMP TRP03,I RESTART SKP * MEMORY ERROR HANDLER ROUTINE * TAKES BAD ADDRESS AND GOOD DATA AND OUTPUTS * TO LED'S OR REMOTE FRONT PANEL, IF IT EXISTS IN SYSTEM * MERR NOP STA ZERRA TEMPORARILY STORE A STB ZERRB AND B XOR B,I ELIMINATE GOOD DATA CLO SET FOR UPPER/LOWER ADDRESS RBL BIT 14 IS MSB SSB STO IT'S IN UPPER HALF RRR 16 SWAP A AND B CLA,RSS START WITH BIT 0 INA COUNT FOR BIT POSITION CPA Z20 END OF BIT CHECK JMP *+6 CLE,SLB,ERB NO CHK FOR BIT & ROTATE JMP *+2 BAD BIT SO DISPLAY JMP *-5 NO SO TRY AGAIN SZB CHK IF MULTI BIT ERROR IOR Z20 YES SO SET LEDS 1XXX SOC CHK FOR UPPER/LOWER IOR Z40 ITS UPPER ALF,ALF PUT DATA IN UPPER HALF IOR Z12 INDICATE MEMORY ERROR JSB DSPLY GO DISPLAY IT ADB MERR ERROR ADDRESS FOR DISPLAY HLT 12B STOP AND DISPLY FP LDA ZERRA GET A LDB ZERRB AND B BACK FROM TEMPORARY STORAGE DSFP HLT 52B A=GOOD DATA,B=ADDR. OF FAILURE JMP MERR+3 GO BACK AND CONT. SKP HED ILLEGAL INTERUPT AND DISPLAY SUBROUTINES * * *ERROR SUBROUTINES * * ERROR HANDLING ROUTINE * ILINT NOP RETURN ADDRESS STA ZERRA SAVE A STB ZERRB SAVE A AND B LIA CIR WAS INTERRUPT FROM MPT? CPA Z5 WAS IT A PARITY ERROR INTERRUPT? JMP ILPRT YES CPA Z7 WAS IT A MEMORY PROTECT INT? RSS YES JMP MPERR NO - PROCESS ERROR LIA VIOLA,C WAS THIS AN EXPECTED MPT INTERRUPT? CPA A.5AD DID DMA.5 CAUSE A VIOLATION? JMP ITSOK YES - IT'S OK MPERR CLC 0,C TURN OFF INTERRUPTS JSB RSTRP RESTORE TRAP CELL LIA CIR GET INTERRUPT REGISTER TO ERROR ALF,ALF MOVE IT TO UPPER HALF IOR Z14 PUT IN LOACATION OF ERROR JSB DSPLY GO DISPLAY IT HLT14 ADB ILINT CREATE ILLEGAL INTERRUPT ADDRESS HLT 14B STOP AND DISPLAY FP LDA ZERRA GET A AND LDB ZERRB B AT INTERRUPT HLT 54B STOP AND DISPLAY FP JMP MPERR+2 LOOP BACK AND CONTINUE DOING * ITSOK STA ILINT SAVE ADDRESS OF "ILLEGAL" INSTRUCTION LDA ZERRA RESTORE A JMP ILINT,I MPT IS OFF - CONTINUE WITH DMA TEST * ILPRT LIA PES GET VIOLATING ADDRESS SSA WAS IT AN INSTR. FETCH? JMP MPERR YES SO PROCESSOR ERROR LDA ZERRA GET A AND JSB MERR GO SERVICE THE MEMORY ERROR SKP * TAKE CONTENTS IN A REGISTER AND DISPLAY TO * LED'S ON COMPUTER. CAUSES FLASHING DISPLAY * THIS ROUTINE IS CALLED BY THE DIFFERENT ERROR * THROUGHOUT THE KERNAL TO DISPLAY SYSTEM FAULT * MESSAGES ON THE LED'S. IT ALSO CHECKS FOR * A FRONT PANEL WHICH IF EXISTS,CAUSES A RETURN * TO THE MAIN PROGRAM FOR DISPLAY TO FRONT PANEL. * DSPLY NOP RETURN ADDRESS SECTION STA B STORE A IN B ALF,ALF SWAP UPPER AND LOWER BYTES AND Z77 MASK OUT LOWER SIX BITS. STA MTSTR SAVE ERROR CODE FOR FP CLA CLEAR A TO CHECK FOR LIA 3,C FRONT PANEL SZA IF A<>0 THEN FRONT PANEL EXISTS JMP HALT GET OUT OF SUBROUTINE TO FP DSPL1 LDA B LOAD A INTO B CCE SET FOR UPPER HALF AND Z177 GET LOWER HALF OTA LEDS OUTPUT TO LEDS ISZ A START TIME LOOP JMP *-1 ISZ A DO IT AGAIN JMP *-1 ISZ A AND AGAIN JMP *-1 ISZ A ONE MORE TIME! JMP *-1 LDA B GET A FROM B ALF,ALF SWAP UPPER AND LOWER HALVES STA B RESTORE A TO B AND Z177 GET OTHER HALF SEZ,CME OR BIT 6 IF E = 1 IOR Z100 INSERT BIT 6 JMP DSPL1+3 GO DO IT AGAIN HALT CLA CLEAR A RRR 4 LOAD S/C FAILURE INTO UPPER BITS A IOR MTSTR OR IN SUBSECTION FAILURE CCB PUT -1 IN B TO CREATE FAILURE ADDRESS JMP DSPLY,I BACK TO MAIN PROGRAM HED MEMORY TEST * * MEMORY ADDRESS TEST * MTSTR NOP START OF MEMORY TEST ROUTINE LDB FADD L00 LDA B PUT IN A FOR GOOD DATA STA B,I STORE IN EACH CPB LADD LOCATION OF AVAILABLE JMP *+3 MEMORY THE ADDRESS INB OF THAT LOCATION JMP L00 LDB FADD L01 LDA B CPA B,I VERIFY MEMORY RSS CONTENTS JSB MERR MEMORY ADDRESS FAILURE CPB LADD JMP *+3 GO ON TO MEMORY PATTERN TEST INB JMP L01 * LDB FADD L00A LDA B CMA STORE IN EACH LOCATION STA B,I THE COMPLEMENTED ADDRESS CPB LADD OF THAT LOCATION JMP *+3 INB JMP L00A LDB FADD L01B LDA B VERIFY EACH LOCATION CMA CPA B,I JMP *+2 JSB MERR CPB LADD JMP *+3 INB JMP L01B SKP * * MEMORY PATTERN TEST * CCA START WITH 177777 L02 LDB FADD L03 STA B,I WRITE PATTERN INB IN A REG IN CPB LADD AVAILABLE MEMORY RSS JMP L03 LDB FADD L04 CPA B,I COMPARE PATTERN READ RSS TO PATTERN WRITTEN JSB MERR MEMORY PATTERN FAILED INB CPB LADD RSS JMP L04 CPA ALT3 IA IT ALT3? JMP NXT00 ALL DONE WITH TEST CPA ALT2 ALT2 DONE? LDA ALT3 LOAD ALT3(152777) CPA ALT1 ALT1 DONE? LDA ALT2 YES. LOAD ALT2(025000) CPA ALT0 ALT0 DONE? LDA ALT1 YES LOAD ALT1 SZA,RSS ALL ZEROES? LDA ALT0 YES,START CHECKERBOARD CPA MD1 IS FIRST TEST DONE? CLA SET TO ALL ZEROES JMP L02 NXT00 EQU * SKP * * WORST CASE PATTERN TEST * LDA FADD LDB FADD L05 STA SAVE AND Z140 WRITE CPA Z140 WORST CLA CASE SZA PATTERN CCA STA B,I IN MEMORY CPB LADD JMP NXT01 INB LDA SAVE INA JMP L05 NXT01 LDA FADD LDB FADD L06 STA SAVE AND Z140 NOW CPA Z140 COMPARE CLA PATTERN SZA CCA CPA B,I RSS JSB MERR MEMORY PATTERN FAILED CPB LADD JMP NXT02 CONTINUE CLA FILL UNUSED MEMORY STA B,I WITH ZEROS INB LDA SAVE INA JMP L06 Z140 OCT 140 * SKP * ADDRESS PARITY TEST * NXT02 CLE START WITH 0 FOR EVEN PARITY LDB FADD FIRST ADDRESS OF AVAILABLE MEMORY L07 LDA B USE A AS A WORKING REG RBL,ERB SAVE ODD OR EVEN FLAG SLA,ARS CME SET ODD OR EVEN FLAG SZA ALL OF ADDRESS DONE? JMP *-3 NO SEZ ODD OR EVEN? CCA,CLE ODD SO SET TO ALL ONES ELB,RBR RESTORE ODD/EVEN FLAG STA B,I PUT IT IN MEMORY CPB LADD JMP NXT03 INB JMP L07 * NXT03 LDB FADD GET STARTING ADDRESS AGAIN L08 LDA B DO THE SAME AS ABOVE RBL,ERB SAVE ODD OR EVEN FLAG SLA,ARS CME SZA JMP *-3 SEZ CCA,CLE ELB,RBR RESTORE ODD/EVEN FLAG CPA B,I JMP *+2 JSB MERR MEMORY FAILED CPB LADD JMP NXT04 INB JMP L08 * NXT04 SEZ,CME,RSS DONE ODD? JMP NXT02+1 NO SKP * DISTURBANCE (SOCCER BALL PATTERN) TEST * CLA START WITH REGULAR PATTERN L09 STA PTGNC CLE L10 CLO L11 LDB FADD GET STARTING ADDRESS L12 JSB PTGN1 GENERATE PATTERN STA B,I PUT PATTRN IN MEMORY CPB LADD IS THIS THE LAST ADDRESS? JMP *+3 YES- MOVE TO CHECK MEMORY INB NO- MOVE TO NEXT LOCATION JMP L12 LDB FADD CHECK PATTERN JUST STORED L13 JSB PTGN1 CPA B,I RSS JSB MERR MEMORY FAILED CPB LADD JMP *+3 INB JMP L13 SOC SET TO DO NEXT PATTERN JMP *+3 STO JMP L11 SEZ JMP *+3 NOW DO COMPLEMENTED PATTERN CCE JMP L10 LDA PTGNC CHECH IF COMPLEMENTED PATTERN DONE? SZA ?? JMP MTSTR,I YES RETURN LDA ZCMA NO GET COMPLEMENT INSTRUCTION JMP L09 AND DO IT SPC 1 PTGN1 NOP CLA SEZ ZCMA CMA SLB CMA BLF,BLF SOS JMP *+4 SSB CLA JMP *+3 SSB,RSS CLA BLF,BLF PTGNC NOP COMPLEMENT INSTRUCTION JMP PTGN1,I RETURN SKP * * PARITY ERROR INTERRUPT TEST * * PEIT LDA Z5 ESTABLISH RETURN STA CNTR STORE IT IN SUBSECTION COUNTER JSB JPTRP ADDRESS WITH PARITY DEF PERT0 MERR,IIN TRAP CEL CLA CLEAR A AND STORE IN STA TEMP0 TEMPORARY REGISTER CLC PES TURN OFF PARITY SYSTEM STF PES CHANGE (SET) SENSE LDA Z1000 START WITH LOC 1000 L20 STA A,I STORE ADDRESS IN ITSELF INA INCREMENT ADDRESS CPA Z2000 IS IT 2000? RSS JMP L20 NO DO AGAIN LDA BADIS LD TEST INSTR. & CHG. STA BADIN SENSE,ST INSTR. CLF PES RESTORE PARITY SENSE LDA Z1000 LOAD STARTING ADDRESS L21 STC PES TURN ON PARITY SYSTEM LDB A,I TRY TO CAUSE INTERRUPT JSB PROER,I DIDN'T OCCUR PERT0 CPA B DID CONTENTS LOAD? RSS JSB PROER,I NO. MERR LIB PES GET VIOLATION ADDR. CPB A IS IT CORRECT? RSS JSB PROER,I NO. MERR STA A,I RESTOR GOOD PARITY TO LOCATION INA INCREMENT ADDR. CPA Z2000 LAST ADDR.? RSS JMP L21 BACK FOR MORE JSB RSTRP RESTORE TRAP CELL SKP * * LDA Z5 LOAD NEW PARITY JSB JPTRP MERR INTERRUPT DEF PERT1 RETURN ADDRESS STC PES ENABLE PARITY SYSTEM TURNED OFF BY INT. CCA FILL A WITH ONES BADIN NOP EXECUTE BAD INSTR. STA BADIN RESTORE GOOD PARITY TO ADDRESS JSB PROER,I DIDN'T CAUSE INTERRUPT PERT1 STA BADIN RESTORE GOOD PARITY TO LOCATION JSB RSTRP RESTORE TRAP CELL TURNED LDA TEMP0 CHECK IF WRITE IS TURNED SZA TO A READ JSB MERR WRITE OCCURRED LIA PES GET VIOLATION ADDR. STC PES TURN ON PARITY SYSTEM SSA,RSS SIGN BIT = 1 (PARITY INT. DURING FETCH?) JSB PROER,I NO ELA,CLE,ERA STRIP OFF SIGN BIT CPA BDN IS IT CORRECT? JMP TST01 GO TEST CPU JSB PROER,I NO. ERROR * * * *NOTE: IF THE STF 5, CLF 5, CLC 5, STC 5 INSTRUCTIONS FAIL AT THIS * POINT, A FAILURE WILL BE INDICATED EITHER BY NO INTERRUPT * OCCURING, OR THE INTERRUPT OCCURRING AT THE WRONG LOCATION * I.E. WRONG PARITY INTERRUPT REGISTER CONTENTS SKP * * STORAGE AND CONSTANTS * MD1 OCT -1 ZM1K OCT -1000 Z4 OCT 4 Z5 OCT 5 Z7 OCT 7 Z10 OCT 10 Z11 OCT 11 Z12 OCT 12 Z14 OCT 14 Z20 OCT 20 Z40 OCT 40 Z77 OCT 77 Z100 OCT 100 Z177 OCT 177 Z777 OCT 777 Z1000 OCT 1000 Z1777 OCT 1777 Z2000 OCT 2000 Z3000 OCT 3000 Z4000 OCT 4000 ZBFA OCT 20000 RSTFD DEF RSTRF DEF RSTRF-2000B+20000B A.5AD DEF DMA.5 PLAD OCT 17777 * ZMXAD OCT 77777 OCT 37777 BAD2 DEF BIOIN BAD3 DEF BDI BAD4 DEF BUI.1 ALT0 OCT 125252 ALT1 OCT 052525 ALT2 EQU Z1000 ALT3 EQU Z3000 PFWCC OCT 177340 DILN0 DEF ILINT DILN1 DEF ILINT-2000B+20000B BDN DEF BADIN BADIS STA TEMP0 TEST INSTRUCTION CKSA EQU Z2000 CKEA DEF *+2 OCT 135741 TWO'S COMPLEMENT OF CHECKSUM FADD NOP LADD NOP AFLG OCT 0,0 START UP FLAGS RSTRF NOP RESTORE FLAG ZERRA EQU SAVE ZERRB EQU RSTR PFWC NOP HED CPU INSTRUCTION TESTS ORG 3777B * TST01 LDA B10 LOAD STATUS AND OTA LEDS SEND TO LEDS * RSS DOES RSS WORK? JSB CPUER,I NO - RSS FAILED * CLA,SZA A=000000 B=XXXXXX E=X OV=X JSB CPUER,I CLA,SZA FAILED * SZA,RSS RSS JSB CPUER,I SZA,RSS FAILED * SSA JSB CPUER,I SSA FAILED * SLA JSB CPUER,I SLA FAILED * SSA,RSS RSS JSB CPUER,I SSA,RSS FAILED * SLA,RSS RSS JSB CPUER,I SLA,RSS FAILED * CMA,SZA A=177777 B=XXXXXX E=X OV=X RSS JSB CPUER,I CMA,SZA FAILED * SZA,RSS JSB CPUER,I SZA,RSS FAILED * SSA RSS JSB CPUER,I SSA FAILED * SLA RSS JSB CPUER,I SLA FAILED * SSA,RSS JSB CPUER,I SSA,RSS FAILED * SLA,RSS JSB CPUER,I SLA,RSS FAILED SKP CLA,SZA A=000000 B=XXXXXX E=X OV=X JSB CPUER,I CLA FAILED * CCA,SZA A=177777 B=XXXXXX E=X OV=X RSS JSB CPUER,I CCA,SZA FAILED SKP * CLB,SZB A=177777 B=000000 E=X OV=X JSB CPUER,I CLB,SZB FAILED(CLB CAN STILL FAIL IF * B IS 0 * SZB,RSS RSS JSB CPUER,I SZB,RSS FAILED * SSB JSB CPUER,I SSB FAILED * SLB JSB CPUER,I SLB FAILED * SSB,RSS RSS JSB CPUER,I SSB,RSS FAILED * SLB,RSS RSS JSB CPUER,I SLB,RSS FAILED * CMB,SZB A=177777 B=177777 E=X OV=X RSS JSB CPUER,I CMB,SZB FAILED * SZB,RSS JSB CPUER,I SZB,RSS FAILED * SSB RSS JSB CPUER,I SSB FAILED * SLB RSS JSB CPUER,I SLB FAILED * SSB,RSS JSB CPUER,I SSB,RSS FAILED * SLB,RSS JSB CPUER,I SLB,RSS FAILED * CLB,SZB A=177777 B=000000 E=X OV=X JSB CPUER,I CLB FAILED SKP * CCB,SZB A=177777 B=177777 E=X OV=X RSS JSB CPUER,I CCB,SZB FAILED * CLE A=177777 B=177777 E=0 OV=X SEZ JSB CPUER,I CLE/SEZ FAILED * CME A=177777 B=177777 E=1 OV=X SEZ RSS JSB CPUER,I CME/SEZ FAILED * SEZ,RSS JSB CPUER,I SEZ,RSS FAILED ON E=1 * CLE A=177777 B=177777 E=0 OV=X SEZ JSB CPUER,I CLE FAIL * SEZ,RSS RSS JSB CPUER,I SEZ,RSS FAIL ON E=0 * CCE A=177777 B=177777 E=1 OV=X SEZ RSS JSB CPUER,I CCE FAILED * CCE SEZ,RSS JSB CPUER,I CCE FAILED - ACTED AS CME * SEZ,CLE,RSS A=177777 B=177777 E=0 OV=X JSB CPUER,I E CLEARED BEFORE SKIP OCCURRED * * SEZ,CCE A=177777 B=177777 E=1 OV=X JSB CPUER,I E SET BEFORE THE SKIP * * CME A=177777 B=177777 E=0 OV=X SEZ,CME A=177777 B=177777 E=1 OV=X JSB CPUER,I E COMPLEMENTED BEFORE SKIP CLE A=177777 B=177777 E=0 OV=X SPC 1 * * * AT THIS POINT, THE FOLLOWING IS TESTED: * * SEZ,CLE,CME,CCE * * CL*,CM*,CC*,SS*,SL*,SZ*,RSS * SKP CLA A=000000 B=177777 E=0 OV=X CPA B.0 RSS JSB CPUER,I CPA FAIL * CPA M1 JSB CPUER,I CPA FAIL * CCA A=177777 B=177777 E=0 OV=X CPA M1 RSS JSB CPUER,I CPA FAIL * CPA B.0 JSB CPUER,I CPA FAIL * CLB A=177777 B=000000 E=0 OV=X CPB B.0 RSS JSB CPUER,I CPB FAIL * CPB M1 JSB CPUER,I CPB FAIL * CCB A=177777 B=177777 E=0 OV=X CPB M1 RSS JSB CPUER,I CPB FAIL * CPB B.0 JSB CPUER,I CPB FAIL * * CP* NOW TESTED SKP LDA B.0 A=000000 B=177777 E=0 OV=X CPA B.0 RSS JSB CPUER,I LDA FAIL * LDA M1 A=177777 B=177777 E=0 OV=X CPA M1 RSS JSB CPUER,I LDA FAIL * LDA M.Z1 A=125252 B=177777 E=0 OV=X CPA M.Z1 RSS JSB CPUER,I LDA FAIL * LDA B.Z0 A=052525 B=177777 E=0 OV=X CPA B.Z0 RSS JSB CPUER,I LDA FAIL * CPB M1 CLA,RSS A=000000 B=177777 E=0 OV=X JSB CPUER,I B WAS MODIFIED DURING LDA * LDB B.0 A=000000 B=000000 E=0 OV=X CPB B.0 RSS JSB CPUER,I LDB FAIL * LDB M1 A=000000 B=177777 E=0 OV=X CPB M1 RSS JSB CPUER,I LDB FAIL * LDB M.Z1 A=000000 B=125252 E=0 OV=X CPB M.Z1 RSS JSB CPUER,I LDB FAIL * LDB B.Z0 A=000000 B=052525 E=0 OV=X CPB B.Z0 RSS JSB CPUER,I LDB FAIL * SEZ JSB CPUER,I E WAS SET BY LD* TESTS CCE,SZA A=000000 B=052525 E=1 OV=X JSB CPUER,I A WAS MODIFIED BY LDB * LD* TESTED AT THIS POINT SKP * * TEST OV INSTRUCTIONS * STO A=000000 B=052525 E=1 OV=1 SOS JSB CPUER,I SOS/STO FAILED SOS JSB CPUER,I CLEAR OCCURRED(SOS C) SOC JMP *+2 JSB CPUER,I SOC FAILED SOS JSB CPUER,I CLEAR OV OCCURRED(SOC C) CLO A=000000 B=052525 E=1 OV=0 SOC JSB CPUER,I CLO/SOC FAILED SOS JMP *+2 SOS JSB CPUER,I SOS FAILED STO A=000000 B=052525 E=1 OV=1 SOS C A=000000 B=052525 E=1 OV=0 JSB CPUER,I SOS C FAILED SOC JSB CPUER,I CLEAR OF SOS C FAILED STO A=000000 B=052525 E=1 OV=1 SOC C A=000000 B=052525 E=1 OV=0 JMP *+2 JSB CPUER,I SOC C FAILED SOC JSB CPUER,I CLEAR OF SOC C FAILED * CHECK REGISTERS FOR CHANGES SZA JSB CPUER,I A MODIFIED CPB B.Z0 RSS JSB CPUER,I B MODIFIED SEZ,CLE,RSS A=000000 B=052525 E=0 OV=0 JSB CPUER,I E WAS CLEARED SKP * * TEST INA WITH E AND OV * E SET WHEN *=177777 AND IN* * OV SET WHEN *=077777 AND IN* * TEST INA STO A=000000 B=052525 E=1 OV=1 INA A=000001 B=052525 E=0 OV=1 RSS JSB CPUER,I INA CAUSED A SKIP TO OCCUR CPA B.1 RSS JSB CPUER,I INA FAILED SEZ,CCE A=000001 B=052525 E=1 OV=1 JSB CPUER,I E WAS SET BY INA SOS C A=000001 B=052525 E=1 OV=0 JSB CPUER,I OV INCORRECTLY SET BY INA * INA A=000002 B=052525 E=1 OV=0 RSS JSB CPUER,I INA CAUSED A SKIP TO OCCUR CPA B.2 RSS JSB CPUER,I INA FAILED SEZ,CLE,RSS A=000002 B=052525 E=0 OV=0 JSB CPUER,I E INCORRECTLY CLEARED BY OV SOC JSB CPUER,I OV INCORRECTLY SET BY INA * CCA A=177777 B=052525 E=0 OV=0 INA A=000000 B=052525 E=1 OV=0 RSS JSB CPUER,I INA CAUSED A SKIP TO OCCUR CPA B.0 RSS JSB CPUER,I INA FAILED SOC JSB CPUER,I OV INCORRECTLY SET BY INA SEZ,CLE,RSS A=000000 B=052525 E =0 OV=0 JSB CPUER,I E WAS NOT SET BY INA SKP LDA MAXP A=077777 B=052525 E=0 OV=0 INA A=100000 B=052525 E=0 OV=1 RSS JSB CPUER,I INA CAUSED A SKIP TO OCCUR CPA MIT15 RSS JSB CPUER,I INA FAILED SOS C A=100000 B=052525 E=0 OV=0 JSB CPUER,I OV WAS NOT SET BY INA SEZ JSB CPUER,I E WAS INCORRECTLY SET BY INA * * DO LOOP FROM 100000 TO 000000 ALOOP INA A=A+1 B=052525 E=0(1 ON EXIT) * OV=0 SOC JSB CPUER,I OV SET DURING LOOP OR INA SKIPPED SEZ,CLE,RSS A=A B=052525 E=0 OV=0 JMP ALOOP CPA B.0 RSS JSB CPUER,I INA FAILED TO EXIT AT PROPER POINT * * DO LOOP FROM 000000 TO 100000 BLOOP INA A=A+1 B=052525 E=0 OV=0 * (OV=1 ON EXIT) SEZ JSB CPUER,I E SET IN LOOP OR INA SKIPPED SOS JMP BLOOP CPA MIT15 RSS JSB CPUER,I FAIL TO EXIT AT CORRECT PLACE IN LOOP * * CHECK B CPB B.Z0 RSS JSB CPUER,I B MODIFIED DURING INA TEST SKP * TEST INB LDA B.Z0 A=052525 B=052525 E=0 OV=1 CLB A=052525 B=000000 E=0 OV=1 INB A=052525 B=000001 E=0 OV=1 RSS JSB CPUER,I INB CAUSED A SKIP TO OCCUR CPB B.1 RSS JSB CPUER,I INB FAILED SEZ,CCE A=052525 B=000001 E=1 OV=1 JSB CPUER,I E WAS SET BY INB SOS C A=052525 B=000001 E=1 OV=0 JSB CPUER,I OV INCORRECTLY SET BY INB * INB A=052525 B=000002 E=1 OV=0 RSS JSB CPUER,I INB CAUSED A SKIP TO OCCUR CPB B.2 RSS JSB CPUER,I INB FAILED SEZ,CLE,RSS A=052525 B=000002 E=0 OV=0 JSB CPUER,I E INCORRECTLY CLEARED BY OV SOC JSB CPUER,I OV INCORRECTLY SET BY INB * CCB A=052525 B=177777 E=0 OV=0 INB A=052525 B=000000 E=1 OV=0 RSS JSB CPUER,I INB CAUSED A SKIP TO OCCUR CPB B.0 RSS JSB CPUER,I INB FAILED SOC JSB CPUER,I OV INCORRECTLY SET BY INB SEZ,CLE,RSS A=052525 B=000000 E=0 OV=0 JSB CPUER,I E WAS NOT SET BY INB SKP LDB MAXP A=052525 B=077777 E=0 OV=0 INB A=052525 B=100000 E=0 OV=1 RSS JSB CPUER,I INB CAUSED A SKIP TO OCCUR CPB MIT15 RSS JSB CPUER,I INB FAILED SOS C A=052525 B=100000 E=0 OV=0 JSB CPUER,I OV WAS NOT SET BY INB SEZ JSB CPUER,I E WAS INCORRECTLY SET BY INB * * * DO LOOP FROM 100000 TO 000000 CLOOP INB A=052525 B=B+1 E=0(1 ON EXIT) OV=0 SOC JSB CPUER,I OV SET DURING LOOP OR INB SKIPPED SEZ,CLE,RSS A=052525 B=B E=0 OV=0 JMP CLOOP CPB B.0 RSS JSB CPUER,I INB FAILED TO EXIT AT PROPER POINT * * DO LOOP FROM 000000 TO 100000 DLOOP INB A=052525 B=B+1 E=0 OV=0(1 ON EXIT) SEZ JSB CPUER,I E SET IN LOOP OR INB SKIPPED SOS C A=052525 B=B E=0 OV=0 JMP DLOOP CPB MIT15 RSS JSB CPUER,I FAIL TO EXIT AT CORRECT PLACE IN LOOP * * CHECK A CPA B.Z0 RSS JSB CPUER,I A MODIFIED DURING INA TEST SKP JMP TSTST * LOC1 NOP SPC 1 TSTST STA LOC1 RSS JSB CPUER,I STA ACTED AS SKIP CPA LOC1 RSS JSB CPUER,I STA FAIL * LDA M.Z1 A=125252 B=100000 E=0 OV=0 STA LOC1 RSS JSB CPUER,I STA ACTED AS SKIP CPA LOC1 RSS JSB CPUER,I STA FAIL * CLA A=000000 B=100000 E=0 OV=0 STA LOC1 RSS JSB CPUER,I STA ACTED AS SKIP CPA LOC1 RSS JSB CPUER,I STA FAIL * CCA A=177777 B=100000 E=0 OV=0 STA LOC1 RSS JSB CPUER,I STA ACTED AS SKIP CPA LOC1 RSS JSB CPUER,I STA FAIL * CPB MIT15 RSS JSB CPUER,I B MODIFIED BY STA SEZ JSB CPUER,I E INCORRECTLY SET BY STA SOC JSB CPUER,I OV INCORRECTLY SET BY STA STB LOC1 RSS JSB CPUER,I STB ACTED AS A SKIP CPB LOC1 RSS JSB CPUER,I STB FAIL SKP LDB M.Z1 A=177777 B=125252 E=0 OV=0 STB LOC1 RSS JSB CPUER,I STB ACTED AS A SKIP CPB LOC1 RSS JSB CPUER,I STB FAIL * CLB A=177777 B=000000 E=0 OV=0 STB LOC1 RSS JSB CPUER,I STB ACTED AS A SKIP CPB LOC1 RSS JSB CPUER,I STB FAIL * CCB A=177777 B=177777 E=0 OV=X STB LOC1 RSS JSB CPUER,I STB ACTED AS A SKIP CPB LOC1 RSS JSB CPUER,I STB FAIL * CPA M1 RSS JSB CPUER,I A MODIFIED BY STB SEZ JSB CPUER,I E WAS IKNCORRECTLY SET BY STB SOC JSB CPUER,I OV WAS INCORRECTLY SET BY STB * ST* TESTED AT THIS POINT SKP * TEST ALL ALU FUNCTIONS AND B.0 A=000000 B=177777 E=0 OV=0 SZA JSB CPUER,I AND FAILED * AND M1 A=000000 B=177777 E=0 OV=0 SZA JSB CPUER,I AND FAILED * IOR M.Z1 A=125252 B=177777 E=0 OV=0 RSS JSB CPUER,I IOR ACTED AS SKIP CPA M.Z1 RSS JSB CPUER,I IOR FAILED * AND M.Z1 A=125252 B=177777 E=0 OV=0 CPA M.Z1 RSS JSB CPUER,I AND FAILED * AND B.Z0 A=000000 B=177777 E=0 OV=0 SZA JSB CPUER,I AND FAILED * IOR M1 A=177777 B=177777 E=0 OV=0 RSS JSB CPUER,I IOR ACTED AS SKIP CPA M1 RSS JSB CPUER,I IOR FAILED * AND M1 A=177777 B=177777 E=0 OV=0 CPA M1 RSS JSB CPUER,I AND FAILED * XOR M1 A=000000 B=177777 E=0 OV=0 SZA JSB CPUER,I XOR FAILED * XOR M1 A=177777 B=177777 E=0 OV=0 CPA M1 RSS JSB CPUER,I XOR FAILED SKP XOR B.Z0 A=052525 B=177777 E=0 OV=0 CPA M.Z1 RSS JSB CPUER,I XOR FAILED * XOR B.Z0 A=177777 B=177777 E=0 OV=0 CPA M1 RSS JSB CPUER,I XOR FAILED * IOR M1 A=177777 B=177777 E=0 OV=0 RSS JSB CPUER,I IOR ACTED AS SKIP CPA M1 RSS JSB CPUER,I IOR FAILED * LDA M.Z1 A=125252 B=177777 E=0 OV=0 IOR B.Z0 A=177777 B=177777 E=0 OV=0 RSS JSB CPUER,I IOR ACTED AS SKIP CPA M1 RSS JSB CPUER,I IOR FAILED * LDA B.Z0 A=052525 B=177777 E=0 OV=0 IOR B.Z0 A=052525 B=177777 E=0 OV=0 RSS JSB CPUER,I IOR ACTED AS SKIP CPA B.Z0 RSS JSB CPUER,I IOR FAILED * XOR B.Z0 A=000000 B=177777 E=0 OV=0 SZA JSB CPUER,I XOR FAILED * * XOR,AND,IOR TESTED * TEST THAT B,E,OV NOT CHANGED CPB M1 RSS JSB CPUER,I B MODIFIED SEZ JSB CPUER,I E INCORRECTLY SET SOC JSB CPUER,I OV INCORRECTLY SET * SKP * * * TEST AD* WITH E AND OV * LDA MAXP A=077777 B=177777 E=0 OV=0 ADA B.1 A=100000 B=177777 E=0 OV=1 CPA MIT15 RSS JSB CPUER,I ADA FAIL SEZ JSB CPUER,I E INCORRECTLY SET SOS C A=100000 B=177777 E=0 OV=0 JSB CPUER,I OV INCORRECTLY SET * ADA MIT15 A=000000 B=177777 E=1 OV=1 SZA JSB CPUER,I ADA FAIL SEZ,CLE,RSS A=000000 B=177777 E=0 OV=1 JSB CPUER,I E WAS NOT SET SOS C A=000000 B=177777 E=0 OV=0 JSB CPUER,I OV WAS NOT SET * ADA B.0 A=000000 B=177777 E=0 OV=0 SZA JSB CPUER,I ADA FAIL CCA,SEZ A=177777 B=177777 E=0 OV=0 JSB CPUER,I E INCORRECTLY SET SOC JSB CPUER,I OV INCORRECTLY SET * ADA M1 A=177776 B=177777 E=1 OV=0 CPA DM2Z RSS JSB CPUER,I ADA FAIL SEZ,CLE,RSS A=177776 B=177777 E=0 OV=0 JSB CPUER,I E WAS NOT SET SOC JSB CPUER,I OV INCORRECTLY SET SKP * LDA MAXP A=077777 B=177777 E=0 OV=0 ADA MAXP A=177776 B=177777 E=0 OV=1 CPA DM2Z RSS JSB CPUER,I ADA FAIL CCA,SEZ A=177777 B=177777 E=0 OV=1 JSB CPUER,I E INCORRECTLY SET SOS C A=177777 B=177777 E=0 OV=0 JSB CPUER,I OV WAS NOT SET * ADA B.1 A=000000 B=177777 E=1 OV=0 SZA JSB CPUER,I ADA FAIL SEZ,INA,RSS A=000001 B=177777 E=1 OV=0 JSB CPUER,I E WAS NOT SET SOC JSB CPUER,I OV INCORRECTLY SET * STO A=000001 B=177777 E=1 OV=1 ADA B.1 A=000002 B=177777 E=1 OV=1 CPA B.2 RSS JSB CPUER,I ADA FAIL SEZ,CLE,RSS A=000002 B=177777 E=0 OV=1 JSB CPUER,I E WAS NOT SET SOS C A=000002 B=177777 E=0 OV=0 JSB CPUER,I OV WAS NOT SET * LDA MAXP A=077777 B=177777 E=0 OV=0 ADA MIT15 A=177777 B=177777 E=0 OV=0 CPA M1 RSS JSB CPUER,I ADA FAIL CLA,SEZ A=000000 B=177777 E=0 OV=0 JSB CPUER,I E INCORRECTLY SET SOC JSB CPUER,I OV INCORRECTLY SET SKP * * E AND OV ARE CHECKED OUT FOR ADA * ADA M1 A=177777 B=177777 E=0 OV=0 CPA M1 RSS JSB CPUER,I ADA FAIL * LDA M.Z1 A=125252 B=177777 E=0 OV=0 ADA M.Z1 A=152524 B=177777 E=1 OV=1 CPA M.Z21 CLE,RSS A=152524 B=177777 E=0 OV=1 JSB CPUER,I ADA FAIL * LDA B.Z0 A=052525 B=177777 E=0 OV=1 ADA B.Z0 A=125252 B=177777 E=0 OV=1 CPA M.Z1 RSS JSB CPUER,I ADA FAIL * * ADA WORKS * CHECK THAT B WAS NOT MODIFIED CMB,CLE,SZB A=125252 B=000000 E=0 OV=1 JSB CPUER,I B WAS NOT 177777 SKP * * TEST ADB WITH E AND OV * CLO A=125252 B=000000 E=0 OV=0 LDB MAXP A=125252 B=077777 E=0 OV=0 ADB B.1 A=125252 B=100000 E=0 OV=1 CPB MIT15 RSS JSB CPUER,I ADB FAIL SEZ JSB CPUER,I E INCORRECTLY SET SOS C A=125252 B=100000 E=0 OV=0 JSB CPUER,I OV INCORRECTLY SET * ADB MIT15 A=125252 B=000000 E=1 OV=1 SZB JSB CPUER,I ADB FAIL SEZ,CLE,RSS A=125252 B=000000 E=0 OV=1 JSB CPUER,I E WAS NOT SET SOS C A=125252 B=000000 E=0 OV=0 JSB CPUER,I OV WAS NOT SET * ADB B.0 A=125252 B=000000 E=0 OV=0 SZB JSB CPUER,I ADB FAIL CCB,SEZ A=125252 B=177777 E=0 OV=0 JSB CPUER,I E INCORRECTLY SET SOC JSB CPUER,I OV INCORRECTLY SET * ADB M1 A=125252 B=177776 E=1 OV=0 CPB DM2Z RSS JSB CPUER,I ADB FAIL SEZ,CLE,RSS A=125252 B=177776 E=0 OV=0 JSB CPUER,I E WAS NOT SET SOC JSB CPUER,I OV INCORRECTLY SET * LDB MAXP A=125252 B=077777 E=0 OV=0 ADB MAXP A=125252 B=177776 E=0 OV=1 CPB DM2Z RSS JSB CPUER,I ADB FAIL CCB,SEZ A=125252 B=177777 E=0 OV=1 JSB CPUER,I E INCORRECTLY SET SOS C A=125252 B=177777 E=0 OV=0 JSB CPUER,I OV WAS NOT SET SKP * ADB B.1 A=125252 B=000000 E=1 OV=0 SZB JSB CPUER,I ADB FAIL SEZ,RSS JSB CPUER,I E WAS NOT SET SOC JSB CPUER,I OV INCORRECTLY SET * STO A=125252 B=000000 E=1 OV=1 LDB B.1 A=125252 B=000001 E=1 OV=1 ADB B.1 A=125252 B=000002 E=1 OV=1 CPB B.2 RSS JSB CPUER,I ADB FAIL SEZ,CLE,RSS A=125252 B=000002 E=0 OV=1 JSB CPUER,I E WAS NOT SET SOS C A=125252 B=000002 E=0 OV=0 JSB CPUER,I OV WAS NOT SET * LDB MAXP A=125252 B=077777 E=0 OV=0 ADB MIT15 A=125252 B=177777 E=0 OV=0 CPB M1 RSS JSB CPUER,I ADB FAIL CLB,SEZ A=125252 B=000000 E=0 OV=0 JSB CPUER,I E INCORRECTLY SET SOC JSB CPUER,I OV INCORRECTLY SET SKP * * E AND OV ARE CHECKED OUT FOR ADB * ADB M1 A=125252 B=177777 E=0 OV=0 CPB M1 RSS JSB CPUER,I ADB FAIL * LDB M.Z1 A=125252 B=125252 E=0 OV=0 ADB M.Z1 A=125252 B=052524 E=1 OV=1 CPB M.Z21 CLE,RSS A=125252 B=052524 E=0 OV=1 JSB CPUER,I ADB FAIL * LDB B.Z0 A=125252 B=052525 E=0 OV=1 ADB B.Z0 A=125252 B=125252 E=0 OV=1 CPB M.Z1 RSS JSB CPUER,I ADB FAIL * * ADB WORKS * CHECK A NOT MODIFIED CPA M.Z1 CCE,RSS A=125252 B=125252 E=1 OV=1 JSB CPUER,I A WAS CHANGED BY ADB INSTRUCTIONS * TEST JUMP INSTRUCTION JMP JMNP1 TRY TO EXECUTE A JUMP JSB CPUER,I DIDN'T EXECUTE JMNP2 JMP JMNP3 TRY TO TO JUMP FORWARD JSB CPUER,I DIDN'T WORK JSB CPUER,I DIDN'T WORK JMNP1 JMP JMNP2 TRY TO JUMP BACK JSB CPUER,I DIDN'T WORK * TEST JSB INSTRUCTION JMNP3 JSB JSB1 RETR1 JSB CPUER,I JSB FAILS TO JUMP JSB1 NOP LDA JSB1 A=XXXXXX B=YYYYYY E=X OV=Y CPA JS1 RSS JSB CPUER,I NUMBER STORED IS NOT CORRECT JSB JSB2 RETR2 JSB CPUER,I JSB FAILS TO JUMP JSB2 NOP LDA JSB2 A=XXXXXX B=YYYYYY E=X OV=Y CPA JS2 RSS JSB CPUER,I NUMBER STORED IS NOT CORRECT * JSB WORKS FOR THESE CASES SKP * * TEST ISZ CLO A=XXXXXX B=YYYYYY E=X OV=0 CLE A=XXXXXX B=YYYYYY E=0 OV=0 LDA M1 A=177777 B=YYYYYY E=0 OV=0 STA ISZL ISZ ISZL JSB CPUER,I FAILURE TO SKIP ON INCREMENT TO 0 SEZ JSB CPUER,I E WAS INCORRECTLY SET SOC JSB CPUER,I OV WAS SET INCORRECTLY LDA MIT15 A=100000 B=YYYYYY E=0 OV=0 STA ISZL CLB A=100000 B=000000 E=0 OV=0 CLA A=000000 B=000000 E=0 OV=0 LOOP1 ISZ A A=A+1 B=000000 E=0 OV=0 NOP ISZ B A=A B=B+1 E=0 OV=0 NOP ISZ ISZL JMP LOOP1 RETURN TO LOOP AGAIN * EXIT TEST LOOP CPA MIT15 RSS JSB CPUER,I A NOT ISZ CORRECT TIMES CPB MIT15 RSS JSB CPUER,I B NOT ISZ CORRECT TIMES CLA A=000000 B=1000000 E=0 OV=0 CPA ISZL RSS JSB CPUER,I ISZL NOT ZERO, SO JUMP INCORRECTLY OCCURRED LOOP2 ISZ A A=A+1 B=YYYYYY E=0 OV=0 JMP *+2 JMP EXIT CPA MIT15 JMP TESN JMP LOOP2 TESN SOC JSB CPUER,I OV WAS SET INCORRECTLY SEZ,CCE A=XXXXXX B=YYYYYY E=1 OV=Y JSB CPUER,I E INCORRECTLY SET JMP LOOP2 EXIT NOP JMP TST02 SKP * CONSTANT AREA FOR PAGE 1 B.0 OCT 0 M1 OCT 177777 M.Z1 OCT 125252 B.Z0 OCT 052525 MIT15 OCT 100000 MAXP OCT 077777 B.1 OCT 1 B.2 OCT 2 M.Z21 OCT 052524 JS1 DEF RETR1 JS2 DEF RETR2 ISZL NOP ISZ USES THIS LOCATION DM2Z DEC -2 SPC 1 * INDIRECT MRG LOCATIONS IND3 DEF MU3A IND5 DEF MU2B IND8 DEF IND9 IND9 NOP IND11 NOP IJMP DEF IJMPR JSB CPUER,I FAILURE TO JUMP INDIRECT PROPERLY SKP ORG 5777B * TEST MRG INDIRECTS TST02 NOP LDA IND1,I A=016161 B=121317 E=1 OV=0 CPA BMU2B RSS JSB CPUER,I INDIRECT LOAD FAILS LDB IND2,I A=016161 B=034344 E=1 OV=0 CPB BMU3A RSS JSB CPUER,I INDIRECT LOAD FAILS CPA BMU2B RSS JSB CPUER,I A MODIFIED BY INDIRECT B LOAD SEZ,RSS JSB CPUER,I E WAS CLEARED BY INDIRECT LOADS SOC JSB CPUER,I OV WAS SET BY INDIRECT LOADS CPA IND4,I RSS JSB CPUER,I INDIRECT COMPARE FAILS CPB IND6,I RSS JSB CPUER,I INDIRECT COMPARE FAILS SEZ,RSS JSB CPUER,I E WAS CLEARED BY INDIRECT COMPARES SOC JSB CPUER,I OV WAS CLEARED BY INDIRECT COMPARES STA IND7,I STB IND10,I CPA BMU2B RSS JSB CPUER,I A MODIFIED DURING INDIRECT STORE CPB BMU3A RSS JSB CPUER,I B MODIFIED DURING INDIRECT STORE CPA IND12,I RSS JSB CPUER,I INDIRECT STA FAILED CPB IND13,I RSS JSB CPUER,I INDIRECT STB FAILED SEZ,RSS JSB CPUER,I E WAS CLEARED BY INDIRECT STORES SOC JSB CPUER,I OV WAS SET BY INDIRECT STORES AND IND2,I A=014140 B=034344 E=1 OV=0 CPA BINX RSS JSB CPUER,I AND INDIRECT FAILED CPB BMU3A RSS JSB CPUER,I B MODIFIED BY INDIRECT AND SEZ,RSS JSB CPUER,I E WAS CLEARED BY INDIRECT AND SOC JSB CPUER,I OV WAS SET BY INDIRECT AND * IOR IND6,I A=034344 B=034344 E=1 OV=0 CPA BMU3A RSS JSB CPUER,I IOR INDIRECT FAILS CPB BMU3A RSS JSB CPUER,I B MODIFIED DURING INDIRECT IOR SOC JSB CPUER,I OV WAS SET BY INDIRECT IOR SEZ,RSS JSB CPUER,I E WAS CLEARED BY INDIRECT IOR * XOR IND1,I A=022225 B=034344 E=1 OV=0 CPA BIND RSS JSB CPUER,I XOR FAILED INDIRECT CPB BMU3A RSS JSB CPUER,I B MODIFIED BY INDIRECT XOR SEZ,RSS JSB CPUER,I E WAS CLEARED BY INDIRECT XOR SOC JSB CPUER,I OV WAS SET BY INDIRECT XOR * JMP IJP,I JSB CPUER,I JUMP FAILS IJSBR NOP LDA IJSBT A=XXXXXX B=YYYYYY E=1 OV=0 CPA IJSBR CCA,RSS A=177777 B=YYYYYY E=1 OV=0 JSB CPUER,I INCORRECT ADDRESS STORED * STA IND7,I ISZ IND14,I JSB CPUER,I FAILURE ON INDIRECT TO ISZ A -1 JMP PGAA4 IJMPR LDA BMU2B A=016161 B=034344 E=1 OV=0 ADA IND1,I A=034342 B=034344 E=1 OV=0 CPA BM4 RSS JSB CPUER,I ADA INDIRECT FAILS CPB BMU3A RSS JSB CPUER,I B MODIFIED DURING ADA INDIRECT SEZ,RSS JSB CPUER,I E WAS CLEARED BY ADA INDIRECT SOC JSB CPUER,I OV WAS SET BY ADA INDIRECT * LDB BMU2B A=034342 B=016161 E=1 OV=0 ADB IND1,I A=034342 B=016161 E=1 OV=0 CPA BM4 RSS JSB CPUER,I A MODIFIED BY ADB INDIRECT CPB BM4 RSS JSB CPUER,I ADB INDIRECT FAILS SEZ,RSS JSB CPUER,I E WAS CLEARED BY ADB INDIRECT SOC JSB CPUER,I OV WAS SET BY ADB INDIRECT * JSB IJSB,I IJSR JSB CPUER,I FAILURE TO JSB INDIRECT JSB CPUER,I FAILURE TO JSB INDIRECT SKP * * TEST BASE PAGE ADDRESSING TECHNIQUES * PGAA4 LDB BTEN A=XXXXXX B=000012 E=X OV=Y CCE A=XXXXXX B=000012 E=1 OV=Y CLO A=XXXXXX B=000012 E=1 OV=0 * BASE LDA TRIED LDA BASEP A=077777 B=000012 E=1 OV=0 CPA BMAXV RSS JSB CPUER,I LDA BASE ADDRESS FAILED CPB BTEN RSS JSB CPUER,I B MODIFIED INCORRECTLY SOC JSB CPUER,I OV WAS INCORRECTLY SET SEZ,RSS JSB CPUER,I E WAS INCORRECTLY CLEARED * BASE CPA TRIED CPA BASEP RSS JSB CPUER,I BASE PAGE ADDRESS OF CPA FAILED CPB BTEN RSS JSB CPUER,I B WAS MODIFIED SOC JSB CPUER,I OV WAS INCORRECTLY SET SEZ,RSS JSB CPUER,I E WAS INCORRECTLY CLEARED * BASE ADDRESS WITH AND AND BAS1P A=0525244 B=000012 E=1 OV=0 CPA B.AN1 RSS JSB CPUER,I BASE PAGE ADDRESSING OF AND FAILS CPB BTEN RSS JSB CPUER,I B WAS INCORRECTLY MODIFIED SOC JSB CPUER,I OV WAS SET INCORRECTLY SEZ,RSS JSB CPUER,I E WAS CLEARED INCORRECTLY * BASE ADDRESSING WITH XOR XOR BAS2P A=025252 B=000012 E=1 OV=0 CPA B.XO1 RSS JSB CPUER,I BASE ADDRESSING OF XOR FAILED CPB BTEN RSS JSB CPUER,I B WAS INCORRECTLY MODIFIED SOC JSB CPUER,I OV WAS SET INCORRECTLY SEZ,RSS JSB CPUER,I E WAS CLEARED INCORRECTLY SKP * BASE PAGE ADDRESSING WITH IOR IOR BAS3P A=077777 B=000012 E=1 OV=0 CPA BMAXV RSS JSB CPUER,I BASE ADDRESSING WITH IOR FAILED CPB BTEN RSS JSB CPUER,I B WAS INCORRECTLY MODIFIED SOC JSB CPUER,I OV WAS SET INCORRECTLY SEZ,RSS JSB CPUER,I E WAS CLEARED INCORRECTLY * BASE ADDRESSING WITH STA STA BAS4P CPA BMAXV RSS JSB CPUER,I A MODIFIED INCORRECTLY CPB BTEN RSS JSB CPUER,I B INCORRECTLY MODIFIED SOC JSB CPUER,I OV WAS SET INCORRECTLY SEZ,RSS JSB CPUER,I E WAS CLEARED INCORRECTLY * TEST ISZ BASE PAGE ADDRESSING ISZ BAS4P RSS JSB CPUER,I INCORRECT LOCATION CHOSEN FOR INCREMENT CPA BMAXV RSS JSB CPUER,I A MODIFIED INCORRECTLY CPB BTEN RSS JSB CPUER,I B MODIFIED INCORRECTLY SEZ,RSS JSB CPUER,I E INCORRECLTY CLEARED SOC JSB CPUER,I OV INCORRECTLY SET * TEST BASE ADDRESSING WITH ADA ADA BAS5P A=100000 B=000012 E=1 OV=0 CPA M.NEG RSS JSB CPUER,I A INCORRECT CPB BTEN RSS JSB CPUER,I B INCORRECTLY CHANGED SEZ,RSS JSB CPUER,I E INCORRECTLY CLEARED SOS C JSB CPUER,I OV INCORRECTLY SET * TEST BASE ADDRESSING WITH STA STA BAS4P CPA AIS1,I RSS JSB CPUER,I INCORRECTLY STORED IN BASE PAGE ADDRESS CPB BTEN RSS JSB CPUER,I B MODIFIED INCORRECTLY SEZ,RSS JSB CPUER,I E INCORRECTLY CLEARED SOC JSB CPUER,I OV INCORRECTLY SET * TEST JMP TO A BASE PAGE ADDRESS JMP .JP IND1 DEF MU2B IND2 DEF IND3,I IND4 DEF IND5,I IND6 DEF MU3A IND7 DEF IND8,I IND10 DEF IND11 IND12 DEF IND9 IND13 DEF IND11 BMU2B OCT 016161 BMU3A OCT 034344 BM4 OCT 034342 IND14 DEF IND9 BINX OCT 014140 IJP DEF IJMP,I IJSB DEF IJSBR JSB CPUER,I FAILURE TO INDIRECT JSB IJSBT DEF IJSR BIND OCT 022225 BMAXV OCT 077777 B.AN1 OCT 052524 BTEN OCT 000012 B.XO1 OCT 025252 M.NEG OCT 100000 AIS1 DEF BAS4P SKP *********************************************************** * TEST JL* *********************************************************** TSTJL CCE A=XXXXXX B=XXXXXX E=1 OV=X STO A=XXXXXX B=XXXXXX E=1 OV=1 LDA JL1 A=125252 B=XXXXXX E=1 OV=1 LDB JL2 A=125252 B=077777 E=1 OV=1 OCT 100600 JLA DEF JMP1N TO LOCATION JZ JSB CPUER,I JLA FAILS TO JUMP JMP1N CPA JAL1 RSS JSB CPUER,I A NOT CORRECTLY LOADED CPB JL2 RSS JSB CPUER,I B WAS MODIFIED SOS C A=ADD(JMP1N) B=077777 E=1 OV=0 JSB CPUER,I OV CLEARED BY JLA SEZ,CLE,RSS A=ADD(JMP1N) B=077777 E=0 OV=0 JSB CPUER,I E WAS CLEARED BY JLA LDA JL1 A=125252 B=077777 E=0 OV=0 OCT 100600 JLA DEF JMP2N TO LOCATION JZ1 JSB CPUER,I JLA FAILS TO JUMP JMP2N CPA JAL2 RSS JSB CPUER,I A NOT CORRECTLY LOADED CPB JL2 RSS JSB CPUER,I B WAS MODIFIED SOC JSB CPUER,I OV SET INCORRECTLY SEZ,CCE A=XXXXXX B=077777 E=1 OV=0 JSB CPUER,I E INCORRECTLY SET STO A=XXXXXX B=077777 E=1 OV=1 LDA JL1 A=125252 B=077777 E=1 OV=1 OCT 104600 JLB DEF JMP3N TO LOCATION JZ2 JSB CPUER,I FAIL TO JUMP JMP3N CPA JL1 RSS JSB CPUER,I A MODIFIED CPB JAL3 RSS JSB CPUER,I B NOT CORRECT SOS C A=125252 B=XXXXXX E=1 OV=0 JSB CPUER,I OV WAS INCORRECTLY CLEARED BY JLB SEZ,CLE,RSS A=125252 B=XXXXXX E=0 OV=0 JSB CPUER,I E WAS INCORRECTLY CLEARED BY JLB LDB JL2 A=125252 B=XXXXXX E=0 OV=0 OCT 104600 JLB DEF JMP4N TO LOCATION JZ3 JSB CPUER,I FAILED TO JUMP JMP4N CPA JL1 RSS JSB CPUER,I A MODIFIED CPB JAL4 RSS JSB CPUER,I B NOT CORRECTLY LOADED BY JLB SEZ JSB CPUER,I E INCORRECTLY SET BY JLB SOC JSB CPUER,I OV INCORRECTLY SET BY JLB JMP ASGAL JUMP TO EXTENDED ASG TEST JSB CPUER,I JUMP FAILS *********************************************************** * JL* TABLE *********************************************************** JL1 OCT 125252 JL2 OCT 077777 JAL1 DEF JZ JAL2 DEF JZ1 JAL3 DEF JZ2 JAL4 DEF JZ3 SKP * THIS PROGRAM IS TO FULLY TEST THE ASG INSTRUCTIONS * BY CYCLING THRU THEM SUCCESSIVELY BY INCREMENTING THE * INSTRUCTION. ASGAL LDA ASG.1 ASG-1 IS 001777 SO +1 =002000 STA ASGIN THE LOCATION OF INSTRUCTION EXECUTION FOR A REG LDB FIRST IS KEPT VALUE IN B REGISTER CLE CLO LDA ZEROA STA OLDE STA OLDOV * * SAVE CURRENT REGISTER * UPD LDA FIRST STA TEM0 STA ATEMP JSB SAVR * * UPDATE THE INSTRUCTION BUT CHECK FOR ROLLOVER * LDA ASGIN ADA ONE STA ASGIN AND MAS11 GETS BIT 11 CPA MAS11 JMP BDOIT FINISH A TEST...NOW DO B REGISTER JSB CHECK SETUP REQUIRED OUTPUT OF INSTRUCTION * * RESTORE ALL REGISTERS,ETC. * JSB RSTOR LDA TEM0 ASGIN NOP INSTRUCTION EXECUTION LOCATION JMP NOASK NO SKIP OCCURRED * * SKIP OCCURS * STA TEM0 JSB SAVR SAVE ROUTINE FOR E AND OV LDA SKIPO CPA ZEROA JSB CPUER,I NO EXPECTED SKIP BUT DID SKIP JMP CHEKZ GOTO CHEK REST OF RESULTS * * NO SKIP DID OCCUR * NOASK STA TEM0 JSB SAVR LDA SKIPO CPA ZEROA JMP CHEKZ JSB CPUER,I ERROR NO SKIP BUT EXPECTED SKIP * * CHECK E OV AND REGISTER CONTENTS * CHEKZ LDA ATEMP CPA TEM0 JMP CHEKO JSB CPUER,I FAILURE-REGISTER NOT CORRECT CHEKO LDA OLDOV CPA OVF JMP CHCKE JSB CPUER,I OV WAS NOT CORRECT CHCKE LDA OLDE CPA EKEEP JMP RESTA JSB CPUER,I E WAS NOT CORRECT * * RESTORE ALL REGISTERS AND GOTO NEXT CODE EXECUTION * RESTA JSB RSTOR CALL REGISTER RESTORE FOR E AND OV LDA TEM0 JMP UPD * * EXEC B REGISTER ASG TESTS * BDOIT LDA BSG.1 IS 005777 STA ASGIN STA BSGIN LDA FIRST CLE CLO LDA ZEROA STA OLDE STA EKEEP ********DO SAME LOOP * THIS PROGRAM IS TO FULLY TEST THE ASG INSTRUCTIONS0 * BY CYCLING THRU THEM SUCCESSIVELY BY INCREMENTING THE * INSTRUCTION. * SAVE CURRENT REGISTER * UPDB LDB FIRST STB ATEMP STB TEM0 JSB SAVR * * UPDATE THE INSTRUCTION BUT CHECK FOR ROLLOVER * LDA ASGIN ADA ONE STA ASGIN STA BSGIN AND MAS12 GETS BIT 12 CPA MAS12 JMP .IOTS,I FINISH B TEST JSB CHECK SETUP REQUIRED OUTPUT OF INSTRUCTION * * RESTORE ALL REGISTERS,ETC. * JSB RSTOR LDB TEM0 BSGIN NOP INSTRUCTION EXECUTION LOCATION JMP NOBSK NO SKIP OCCURRED * * SKIP OCCURS * STB TEM0 JSB SAVR SAVE ROUTINE FOR E AND OV LDA SKIPO CPA ZEROA JSB CPUER,I NO EXPECTED SKIP BUT DID SKIP JMP BHEKZ GOTO BHEK REST OF RESULTS * * NO SKIP DID OCCUR * NOBSK STB TEM0 JSB SAVR LDA SKIPO CPA ZEROA JMP BHEKZ JSB CPUER,I ERROR NO SKIP BUT EXPECTED SKIP * * CHECK E OV AND REGISTER CONTENTS * BHEKZ LDA ATEMP CPB TEM0 JMP BHEKO JSB CPUER,I FAILURE-REGISTER NOT CORRECT BHEKO LDA OLDOV CPA OVF JMP BHCKE JSB CPUER,I OV WAS NOT CORRECT BHCKE LDA OLDE CPA EKEEP JMP RESTB JSB CPUER,I E WAS NOT CORRECT * * RESTORE ALL REGISTERS AND GOTO NEXT CODE EXECUTION * RESTB JSB RSTOR CALL REGISTER RESTORE FOR E AND OV LDB TEM0 JMP UPDB * * EXEC B REGISTER ASG TESTS * SAVR NOP SOC JMP OVK1 LDA ZEROA JMP STOOU OVK1 LDA INVE STOOU STA OVF SEZ JMP EK1 LDA ZEROA JMP STOOE EK1 LDA INVE STOOE STA EKEEP JMP SAVR,I RSTOR NOP LDA OVF CPA INVE JMP OEQU1 CLO JMP CKE OEQU1 STO CKE LDA EKEEP CPA INVE JMP EEQU1 CLE JMP RSTOR,I EEQU1 CCE JMP RSTOR,I * * AREA FOR COMMON VARIABLES * ASG.1 OCT 001777 BSG.1 OCT 005777 FIRST OCT 125252 MAS11 OCT 004000 MAS12 OCT 010000 ZEROA OCT 000000 INVE OCT 177777 ONE OCT 1 *TEMP DATA SITES OVF OCT 0 EKEEP OCT 0 TEM0 OCT 0 * UPDATA SITES SKIPO OCT 0 OLDE OCT 0 OLDOV OCT 0 ATEMP OCT 0 * SUBR CHECKR IS TO DETERMINE WHAT THE RESULTS OF THE * ASG INSTRUCTION WILL DO TO THE REGISTER,E , OV, AND * SKIPPING. IT DEPENDS ON BEING CALLED WHEN * THE FOLLOWING IS AVAILABLE IN THE REGISTERS: * ATEMP:CONTAINS THE OLD REGISTER CONTENTS * OLDE :CONTAINS THE OLD E VALUE * OLDOV:CONTAINS THE OLD OV VALUE * * UPON LEAVING, ALL OF THESE ARE UPDATED CHECK NOP LDA ZEROA LOAD A WITH ZERO STA SKIPO CLEAR EXPECTED SKIP OUTPUT LDA ASGIN GETS THE INSTRUCTION TO EXECUTE AND MSK98 GETS CME,CLE,CCE BITS CPA MSK98 JMP ASCCR IS CC* CPA MSK9 JMP ASCMR IS CM* CPA MSK8 JMP ASCLR IS CL* JMP JUM1 NO CC*,CM*,CL* ASCCR LDA INVE CC* REGISTER JMP SAVAX ASCMR LDA ATEMP LOADS OLD REGISTER XOR INVE COMPLEMENTS IT JMP SAVAX ASCLR LDA ZEROA SAVAX STA ATEMP STORES MODIFIED REGISTER FOR LATER USE * * JUM1 LDA ASGIN GETS INSTRUCTION TO EXECUTE AND MSK50 BITS 5 AND 0 TO CHECK SEZ AND RSS CPA MSK50 JMP SEZRS IS SEZ AND RSS CPA MSK5 COMPARE TO FIND ONLY SEZ JMP ASSEZ SEZ ONLY JMP JUM2 SEZRS LDA OLDE LOADS OLD VALUE OF E CPA INVE ISZ SKIPO INCREMENT SO SKIP IS INDICATED JMP JUM2 ASSEZ LDA OLDE CPA INVE JMP JUM2 E IS 1 SO NO SKIP ISZ SKIPO E IS 0 SO SKIP * BEGIN TO UPDATE THE E REQUIRED JUM2 LDA ASGIN LOAD INSTRUCTION FOR DECODE AND MSK76 GET BITS FOR E CHANGE CPA MSK76 JMP ASCCE IT IS CCE CPA MSK7 JMP ASCME IT IS CME CPA MSK6 JMP ASCLE IT IS CLE JMP JUM3 NO E UPDATE REQUIRED ASCCE LDA INVE LOAD A WITH 177777 TO CCE JMP SAVEX ASCME LDA OLDE XOR INVE DO THE CME JMP SAVEX ASCLE LDA ZEROA THIS IS TO CLEAR E SAVEX STA OLDE E SAVE LOCATION * * CHECK THE INSTRUCTION FOR RSS * JUM3 LDA ASGIN LOAD INSTRUCTION FOR DECODE AND MSK0 GET RSS BIT CPA ZEROA CHECKS FOR ZERO JMP NORSS NOT AN RSS IN THE INSTRUCTION * * RSS OCCURS-CHECK FIRST FOR SS* AND SL* THEN EACH ALONE * LDA ASGIN LOADS INSTRUCTION FOR DECODE AND MSK43 CHECK FOR SS* AND SL* CPA MSK43 JMP SSSLR SS* AND SL* OCCUR TOGETHER CPA MSK4 JMP ASSS SS* OCCURS CPA MSK3 JMP ASSL SL* OCCURS JMP JUM4 NO SKIP OF TYPE SS* OR SL* OCCURS SSSLR LDA ATEMP LOADS OLD REGISTER AND MSKF0 MASK OFF BITS 15 AND 0 CPA MSKF0 ISZ SKIPO BITS 15 AND 0 WERE 1 SO SETUP FOR SKIP JMP JUM4 ASSS LDA ATEMP AND MSKF MASK BIT 15 CPA MSKF ISZ SKIPO BIT 15 IS 1 SO SETUP FOR SKIP JMP JUM4 ASSL LDA ATEMP AND MSK0 CPA MSK0 CHECK IF BIT0 IS A 1 ISZ SKIPO BIT 0 IS 1 SO SETUP FOR THE SKIP JMP JUM4 * * NO RSS BUT STILL CHECK FOR SL* AND SS* * NORSS LDA ASGIN LOADS THE INSTRUCTION FOR DECODING AND MSK3 CPA ZEROA JMP CHKSS NO SL* OCCURRED LDA ATEMP AND MSK0 CPA ZEROA ISZ SKIPO SL* AND BIT0=0 SO SETUP THE SKIP CHKSS LDA ASGIN AND MSK4 CPA ZEROA JMP JUM4 NO SS* OCCURRED LDA ATEMP AND MSKF CPA ZEROA ISZ SKIPO SS* AND BIT15=0 SO SETUP FOR SKIP * * DO THE IN* IF IT OCCURRED * JUM4 LDA ASGIN AND MSK2 CPA ZEROA JMP JUM6 NO IN* TO OCCUR * RESTORE OV AND E PRIOR TO IN* LDA OLDE CPA INVE JMP EZ1 CLE JMP CK0 EZ1 CCE CK0 LDA OLDOV CPA INVE JMP OVZ1 CLO JMP CK1 OVZ1 STO CK1 LDA ATEMP ADA ONE ADDS ONE TO SIMULATE IN* STA ATEMP UPDATE REGISTER CONTENTS SEZ JMP E1Z1 LDA ZEROA JMP STORE E1Z1 LDA INVE STORE STA OLDE UPDATE E REGISTER SOC JMP OV1Z1 LDA ZEROA JMP STORO OV1Z1 LDA INVE STORO STA OLDOV * * CHECK FOR SZ* AND RSS * JUM6 LDA ASGIN AND MSK10 CPA MSK10 JMP SZARS SZ* AND RSS OCCUR CPA MSK1 JMP ASSZA ONLY SZ* OCCURS JMP JUM7 SZARS LDA ATEMP CPA ZEROA JMP JUM7 ISZ SKIPO SZ* AND RSS AND REGISTER NOT ZERO SO SKIP JMP JUM7 ASSZA LDA ATEMP CPA ZEROA ISZ SKIPO SZA AND REGISTER IS ZERO SO SKIP SETUP * * CHECK FOR ONLY RSS * JUM7 LDA ASGIN AND MSKAB MASK OFF 000073 CPA MSK0 ONLY BIT 0 IS 1 ISZ SKIPO ONLY AN RSS SO UNCONDITIONAL SKIP * * RETURN SINCE ALL PROGRAM UPDATING HAS OCCURRED * AS REQUIRED. ATEMP,SKIPO,OLDE AND OLDOV * RETURN WITH REGISTER,SKIP,E AND OV INFORMATION * AS TO WHAT THE INSTRUCTION WAS SUPPOSED TO HAVE DONE JMP CHECK,I RETURN VIA INDIRECT MSK98 OCT 001400 MSK9 OCT 001000 MSK8 OCT 000400 MSK76 OCT 000300 MSK7 OCT 000200 MSK6 OCT 000100 MSK50 OCT 000041 MSK5 OCT 000040 MSK43 OCT 000030 MSK4 OCT 000020 MSK3 OCT 000010 MSK2 OCT 000004 MSK10 OCT 000003 MSK1 OCT 000002 MSKF0 OCT 100001 MSKF OCT 100000 MSKAB OCT 000073 MSK0 OCT 000001 SKP ORG 7777B * SRG DIAGNOSTIC * * TST03 NOP LDA NUMT LOADS NUMBER OF TESTS STA TNUMT STORES IN TEMPORARY LDA APTR LOADS TABLE POINTER STA TEMPC STORES INTO TEMPORARY LDB VALUE LOOPI LDA TEMPC,I LOADS NEXT INSTRUCTION STA *+14 STORE BEFORE EXECUTION ISZ TEMPC LDA TEMPC LOADS POINTER INA POINTER NOW TO ELOAD VARIABLE INA LDA A,I LOADS ELOAD VALUE AND ELOAD GETS E LOAD BIT OUT SZA JMP ETO1 CLE E MADE TO BE 0 JMP DOIT ETO1 CCE E MADE TO BE 1 DOIT LDA TEMPC,I LOAD CONTENTS OF A ISZ TEMPC * NOTE THAT NO SKIP WILL NORMALLY OCCUR AS DATA WILL NEVER BE * PLACED SUCH THAT TEMPC=XXX(1777) SO THAT XXX(0) CAN OCCUR NOP INSTRUCTION LOCATION JMP NOSKP NO SKIP OCCURRED BY SRG INSTRUCTION JSB CHEKA SKIP OCCURRED-CHECK A CONTENTS ISZ TEMPC JSB GETSK LOADS E,SKIP,OV INFORMATION TO A * ANDS WITH SKIP SO ONLY SKIP INFO REMAINS SZA,RSS CHECKS WHETHER SKIP SHOULD HAVE OCCURRED JSB CPUER,I SKIP SHOULD NOT OCCUR BUT DID JMP CONT CONTINUE TEST NOSKP JSB CHEKA NO SKIP OCCURRED-CHECK A CONTENTS ISZ TEMPC JSB GETSK GET SKIP INFORMATION SZA CHECK WHETHER SKIP SHOULD HAVE OCCURRED JSB CPUER,I SKIP SHOULD HAVE OCCURRED BUT DID NOT CONT CPB VALUE COMPARE THAT B NOT MODIFIED RSS JSB CPUER,I B NOT CORRECT JSB EOVCK JUMP TO CHECK E AND OV RESULTS ISZ TEMPC INCREMENTS EX,SKIP,OV PCINTER * NOTE THAT IN NEITHER CASE DOES MEMORY ROLLOVER OCCUR * SINCE DATA IS NEVER IN THE LAST LOCATION IN MEMORY ISZ TNUMT CHECK IF ALL TESTS DONE JMP LOOPI NO-GO DO ANTOHER TEST * * DO ALL TESTS AGAIN, BUT WITH B REGISTER * LDA NUMT LOADS NUMBER OF TESTS STA TNUMT STORES IN TEMPORARY LDA APTR LOADS A POINTER STA TEMPC STORES INTO TEMPORARY LOOPB LDA TEMPC,I LOADS NEXT INSTRUCTION IOR BBIT ADDS B INSTRUCTION BIT ISZ TEMPC STA *+14 STORE BEFORE EXECUTION LDA TEMPC LOADS POINTER INA POINTER NOW TO E LOAD INA LDA A,I LOADS E INFO AND ELOAD FINDS E LOAD BIT SZA JMP ETO1B CLE E MADE TO 0 JMP DOITB ETO1B CCE DOITB LDA VALUE LOADS A CONTENTS LDB TEMPC,I LOADS B CONTENTS ISZ TEMPC INCREMENT POINTER * NOTE THAT NO SKIP WILL NORMALLY OCCUR AS DATA WILL NEVER BE * PLACED SUCH THAT TEMPC=XXX(1777) SO THAT XXX(0) CAN OCCUR NOP INSTRUCTION LOCATION JMP NBSKP NO SKIP OCCURRED BY SRG INSTRUCTION JSB CHEKB SKIP OCCURRED-CHECK B CONTENTS ISZ TEMPC CPA VALUE SEE IF A WAS MODIFIED RSS JSB CPUER,I A IS NOT CORRECT JSB GETSK LOADS E,SKIP,OV INFORMATION TO A * ANDS WITH SKIP SO ONLY SKIP INFO REMAINS SZA,RSS CHECKS WHETHER SKIP SHOULD HAVE OCCURRED JSB CPUER,I SKIP SHOULD NOT OCCUR BUT DID JMP CONTB CONTINUE TEST NBSKP JSB CHEKB NO SKIP OCCURRED-CHECK B CONTENTS ISZ TEMPC CPA VALUE SEE IF A MODIFIED RSS JSB CPUER,I A IS NOT CORRECT JSB GETSK GET SKIP INFORMATION SZA CHECK WHETHER SKIP SHOULD HAVE OCCURRED JSB CPUER,I SKIP SHOULD HAVE OCCURRED BUT DID NOT CONTB JSB EOVCK JUMP TO CHECK E AND OV RESULTS ISZ TEMPC INCREMENTS EX,SKIP,CV PCINTER * NOTE THAT IN NEITHER CASE DOES MEMORY ROLLOVER OCCUR * SINCE DATA IS NEVER IN THE LAST LOCATION IN MEMORY ISZ TNUMT CHECK IF ALL TESTS DONE JMP LOOPB NO-GO DO ANTOHER TEST * * DO ALL TESTS AGAIN, BUT WITH B REGISTER * JMP TST04 JUMP TO THE NEXT TEST SECTION CHEKA NOP CPA TEMPC,I COMPARE A WITH EXPECTED RESULTS JMP CHEKA,I RETURN-A IS CORRECT JSB CPUER,I A IS NOT CORRECT CHEKB NOP CPB TEMPC,I COMPARE B WITH EXPECTED RESULTS JMP CHEKB,I RETURN-B IS CORRECT JSB CPUER,I B IS NOT CORRECT GETSK NOP LDA TEMPC,I LOADS E,SKIP,OV EXPECTED RESULTS AND SKIPS ANDS WITH 077776 TO GET SKIP RESULT JMP GETSK,I RETURN TO TEST BODY EOVCK NOP LDA TEMPC,I A GETS EX,SKIP,OV RESULT SSA SKIP ON E RESULT JMP EIS1 E SUPPOSED TO BE 1 SEZ CHECK RESULT OF E(E SUPPOSED TO BE 0) JSB CPUER,I E IS 1,SUPPOSED TO BE 0 JMP TOV JUMP TO OV CHECK EIS1 SEZ,RSS CHECK E RESULT(E SUPPOSED TO BE 1) JSB CPUER,I E IS 0,SUPPOSED TO BE 1 TOV SLA,RSS CHECK OV JMP OVIS0 OV SUPP OSED TO BE 0 SOC OV SUPPOSED TO BE 1,CHECK ACTUAL RESULTS JMP OUTS OV IS CORRECT JSB CPUER,I OV IS 0,SUPPOSED TO BE 1 OVIS0 SOC OV SUPPOSED TO BE 0,CHECK ACTUAL JSB CPUER,I OV IS 1,SUPPOSED TO BE 0 OUTS JMP EOVCK,I RETURN TO MAIN TEST * CONSTANTS FOLLOW NUMT DEC -201 NUMBER OF TESTS IN SRG APTR DEF TABL1 POINTER TO A RESULTS TEMPC OCT 0 TEMPORARY-HOLDS PTR FOR A TNUMT OCT 0 TEMPORARY-HOLDS 2 COMP OF NUMBER TESTS LEFT SKIPS OCT 077774 SKIP MASK ELOAD OCT 000002 E LOAD MASK BBIT OCT 004000 BIT TO AND WITH INSTRUCTION TO GET B VALUE OCT 045273 VALUE TO BE KEPT IN NONUSED REGISTER SKP SPC 5 ************************** * SRG TABLE DESCRIPTION * ************************** SPC 1 * WORD 1. INSTRUCTION * WORD 2. REGISTER LOAD * WORD 3. REGISTER RESULT * WORD 4. EXECUTION INFORMATION * BIT 15: E RESULT * BIT 14-2: SKIP IF 1'S, NO SKIP IF 0'S * BIT 1 : E LOAD * BIT 0 : O RESULT SKP ************************** * SRG TEST TABLES FOLLOW * *************************** TABL1 ALF OCT 131750 OCT 037213 OCT 100002 ALF,ALF OCT 037213 OCT 105476 OCT 100002 ALF,SLA OCT 105476 OCT 131750 OCT 177776 ALF,CLE OCT 131750 OCT 037213 OCT 000002 ALF,SLA OCT 037213 OCT 164263 OCT 100002 ALF,CLE,SLA OCT 164263 OCT 105476 OCT 077776 CLE,ALF OCT 105476 OCT 131750 OCT 000002 SLA,ALF OCT 131750 OCT 037213 OCT 177776 SLA,ALF OCT 037213 OCT 164263 OCT 100002 CLE,SLA,ALF OCT 164263 OCT 105476 OCT 000002 CLE,SLA,ALF OCT 105476 OCT 131750 OCT 077776 ALF,CLE,ALF OCT 131750 OCT 164263 OCT 000002 SKP ALF,SLA,ALF OCT 164263 OCT 131750 OCT 177776 ALF,CLE,SLA,ALF OCT 131750 OCT 164263 OCT 000002 ALF,SLA,ALF OCT 164263 OCT 131750 OCT 177776 ALF,ALF OCT 131750 OCT 164263 OCT 100002 ALF,CLE,SLA,ALF OCT 164263 OCT 131750 OCT 077776 RAL OCT 131750 OCT 063721 OCT 100002 RAL,RAL OCT 063721 OCT 117505 OCT 100002 RAL,SLA OCT 117505 OCT 037213 OCT 100002 RAL,CLE OCT 037213 OCT 076426 OCT 000002 RAL,SLA OCT 076426 OCT 175054 OCT 177776 RAL,CLE,SLA OCT 175054 OCT 172131 OCT 000002 CLE,RAL OCT 172131 OCT 164263 OCT 000002 SKP SLA,RAL OCT 164263 OCT 150547 OCT 100002 RAL,RAL OCT 150547 OCT 042637 OCT 100002 SLA,RAL OCT 042637 OCT 105476 OCT 100002 CLE,SLA,RAL OCT 105476 OCT 013175 OCT 077776 CLE,SLA,RAL OCT 013175 OCT 026372 OCT 000002 RAL,CLE,RAL OCT 026372 OCT 131750 OCT 000002 RAL,SLA,RAL OCT 131750 OCT 147642 OCT 100002 RAL,CLE,SLA,RAL OCT 147642 OCT 037213 OCT 000002 RAL,SLA,RAL OCT 037213 OCT 175054 OCT 177776 RAL,CLE,SLA,RAL OCT 175054 OCT 164263 OCT 000002 RAR OCT 131750 OCT 054764 OCT 100002 RAR,SLA OCT 054764 OCT 026372 OCT 177776 SKP RAR,SLA OCT 026372 OCT 013175 OCT 100002 SLA,RAR OCT 013175 OCT 105476 OCT 100002 SLA,RAR OCT 105476 OCT 042637 OCT 177776 CLE,SLA,RAR OCT 042637 OCT 121317 OCT 000002 RAR,CLE,RAR OCT 121317 OCT 164263 OCT 000002 RAR,RAR OCT 164263 OCT 175054 OCT 100002 CLE,SLA,RAR OCT 175054 OCT 076426 OCT 077776 RAR,SLA,RAR OCT 076426 OCT 117505 OCT 100002 RAR,SLA,RAR OCT 117505 OCT 063721 OCT 177776 RAR,CLE,SLA,RAR OCT 063721 OCT 054764 OCT 077776 RAR,CLE,SLA OCT 054764 OCT 026372 OCT 077776 RAR,CLE,SLA,RAR OCT 026372 OCT 105476 OCT 000002 SKP RAR,CLE OCT 105476 OCT 042637 OCT 000002 CLE,RAR OCT 042637 OCT 121317 OCT 000002 ARS OCT 131750 OCT 154764 OCT 100002 ARS,ARS OCT 154764 OCT 173175 OCT 100002 SLA,ARS OCT 173175 OCT 175476 OCT 100002 SLA,ARS OCT 175476 OCT 176637 OCT 177776 CLE,ARS OCT 176637 OCT 177317 OCT 000002 ARS,CLE OCT 177317 OCT 177547 OCT 000002 ARS,CLE,ARS OCT 177547 OCT 177731 OCT 000002 ARS,SLA OCT 177731 OCT 177754 OCT 177776 CLE,SLA,ARS OCT 046027 OCT 023013 OCT 000002 ARS,SLA OCT 023013 OCT 011405 OCT 100002 SKP ARS,CLE,SLA OCT 011405 OCT 004602 OCT 077776 CLE,SLA,ARS OCT 004602 OCT 002301 OCT 077776 ARS,SLA,ARS OCT 005252 OCT 001252 OCT 100002 ARS,CLE,SLA,ARS OCT 001252 OCT 000252 OCT 000002 ARS,SLA,ARS OCT 000252 OCT 000052 OCT 100002 ARS,CLE,SLA,ARS OCT 000052 OCT 000012 OCT 000002 ALS OCT 046027 OCT 014056 OCT 100002 ALS,ALS OCT 014056 OCT 060270 OCT 100002 ALS,CLE OCT 131750 OCT 163720 OCT 000002 ALS,SLA OCT 046027 OCT 014056 OCT 177776 CLE,ALS OCT 014056 OCT 030134 OCT 000002 SLA,ALS OCT 046027 OCT 014056 OCT 100002 SKP SLA,ALS OCT 014056 OCT 030134 OCT 177776 CLE,SLA,ALS OCT 131750 OCT 163720 OCT 077776 ALS,CLE,SLA OCT 163720 OCT 147640 OCT 077776 CLE,SLA,ALS OCT 046027 OCT 014056 OCT 000002 ALS,CLE,ALS OCT 014056 OCT 060270 OCT 000002 ALS,SLA,ALS OCT 046027 OCT 030134 OCT 177776 ALS,CLE,SLA,ALS OCT 046027 OCT 030134 OCT 077776 ERA OCT 046027 OCT 123013 OCT 100002 SLA,ERA OCT 123013 OCT 151405 OCT 100002 ERA,SLA OCT 151405 OCT 164602 OCT 177776 ERA,SLA OCT 164602 OCT 172301 OCT 000002 ERA,CLE OCT 172301 OCT 075140 OCT 000000 SKP ERA,CLE,SLA OCT 073211 OCT 035504 OCT 077774 ERA,CLE,SLA OCT 004723 OCT 102351 OCT 2 SLA,ERA OCT 075140 OCT 036460 OCT 077774 CLE,ERA OCT 036460 OCT 017230 OCT 000000 CLE,SLA,ERA OCT 017230 OCT 007514 OCT 077774 ERA,SLA,ERA OCT 007514 OCT 001723 OCT 077774 ERA,ERA OCT 001723 OCT 100364 OCT 100000 CLE,SLA,ERA OCT 100364 OCT 040172 OCT 077776 ERA,SLA,ERA OCT 040172 OCT 010036 OCT 100000 CLE,SLA,ERA OCT 010036 OCT 004017 OCT 077776 ERA,CLE,ERA OCT 004017 OCT 001003 OCT 100000 ERA,CLE,SLA,ERA OCT 001003 OCT 040200 OCT 100002 SKP ERA,CLE,SLA,ERA OCT 052725 OCT 052565 OCT 077776 ELA OCT 046027 OCT 114057 OCT 000002 ELA,SLA OCT 114057 OCT 030136 OCT 177774 ELA,SLA OCT 030136 OCT 060275 OCT 000002 SLA,ELA OCT 060275 OCT 140572 OCT 000000 ELA,CLE OCT 140572 OCT 101364 OCT 000000 ELA,CLE,SLA OCT 101364 OCT 002750 OCT 077774 CLE,ELA OCT 002750 OCT 005720 OCT 000002 SLA,ELA OCT 005720 OCT 013640 OCT 077774 CLE,SLA,ELA OCT 013640 OCT 027500 OCT 077776 ELA,ELA OCT 027500 OCT 136400 OCT 000000 ELA,SLA,ELA OCT 136400 OCT 172001 OCT 077774 SKP CLE,SLA,ELA OCT 172001 OCT 164002 OCT 100002 ELA,CLE,SLA,ELA OCT 164002 OCT 120012 OCT 100002 ELA,CLE,ELA OCT 120012 OCT 100052 OCT 000002 ELA,CLE,SLA,ELA OCT 100052 OCT 000250 OCT 077774 ELA,SLA,ELA OCT 000250 OCT 001242 OCT 000002 SKP * NOP CONDITIONS NOP OCT 131750 OCT 131750 OCT 000000 NOP OCT 046027 OCT 046027 OCT 100002 * ALF NOP OCT 000707 OCT 131750 OCT 131750 OCT 100002 OCT 000707 OCT 046027 OCT 046027 OCT 000000 *ALR NOP OCT 000404 OCT 131750 OCT 131750 OCT 000000 OCT 000404 OCT 046027 OCT 046027 OCT 100002 * ALS NOP (SEE NORMAL NOP-000000) * ARS NOP OCT 000101 OCT 131750 OCT 131750 OCT 100002 OCT 000101 OCT 046027 OCT 046027 OCT 000000 * ELA NOP OCT 000606 OCT 131750 OCT 131750 OCT 100000 OCT 000606 OCT 046027 OCT 046027 OCT 000002 * ERA NOP OCT 000505 OCT 131750 OCT 131750 OCT 000002 OCT 000505 OCT 046027 OCT 046027 OCT 100000 SKP * RAL NOP OCT 000202 OCT 131750 OCT 131750 OCT 100002 OCT 000202 OCT 046027 OCT 046027 OCT 000000 * RAR NOP OCT 000303 OCT 131750 OCT 131750 OCT 100002 OCT 000303 OCT 046027 OCT 046027 OCT 000000 * SRG CLE OCT 000040 OCT 131750 OCT 131750 OCT 000002 OCT 000040 OCT 046027 OCT 046027 OCT 000000 * SRG SLA OCT 000010 OCT 131750 OCT 131750 OCT 077774 OCT 000010 OCT 046027 OCT 046027 OCT 100002 SKP * TEST MULTIPLE COMBINATIONS ALS,CLE,SLA,ARS OCT 054737 OCT 014737 OCT 077776 ALS,CLE,SLA,RAL OCT 063647 OCT 117234 OCT 077776 ALS,CLE,SLA,RAR OCT 130267 OCT 070267 OCT 077776 ALS,CLE,SLA,ALR OCT 163437 OCT 016174 OCT 077776 ALS,CLE,SLA,ERA OCT 126707 OCT 066707 OCT 077776 ALS,CLE,ERA OCT 126707 OCT 066707 OCT 000002 ALS,CLE,SLA,ELA OCT 130563 OCT 142714 OCT 177776 ALS,CLE,SLA,ALF OCT 064731 OCT 035445 OCT 077776 ARS,CLE,SLA,ALS OCT 130567 OCT 130566 OCT 000002 ARS,CLE,SLA,RAL OCT 130564 OCT 130565 OCT 077776 ARS,CLE,SLA,RAR OCT 103566 OCT 160735 OCT 000002 ARS,CLE,SLA,ALR OCT 165775 OCT 065774 OCT 077776 SKP ARS,CLE,SLA,ERA OCT 115467 OCT 063315 OCT 100002 ARS,CLE,SLA,ELA OCT 114357 OCT 114356 OCT 100002 ARS,CLE,SLA,ALF OCT 130662 OCT 106635 OCT 000002 RAL,CLE,SLA,ALS OCT 156265 OCT 171326 OCT 000002 RAL,CLE,SLA,ARS OCT 053564 OCT 153564 OCT 077776 RAL,CLE,SLA,RAR OCT 105345 OCT 105345 OCT 000002 RAL,CLE,SLA,ALR OCT 130635 OCT 043166 OCT 000002 RAL,CLE,SLA,ERA OCT 135725 OCT 035725 OCT 100002 RAL,CLE,SLA,ELA OCT 156075 OCT 070366 OCT 100002 RAL,CLE,SLA,ALF OCT 025407 OCT 060345 OCT 077776 RAR,CLE,SLA,ALS OCT 053275 OCT 153274 OCT 077776 RAR,CLE,SLA,ARS OCT 035107 OCT 147221 OCT 000002 SKP RAR,CLE,SLA,RAL OCT 135171 OCT 135171 OCT 077776 RAR,CLE,SLA,ALR OCT 135171 OCT 035170 OCT 077776 RAR,CLE,SLA,ERA OCT 135073 OCT 067216 OCT 100002 RAR,CLE,SLA,ELA OCT 131755 OCT 131754 OCT 177776 RAR,CLE,SLA,ALF OCT 135171 OCT 151715 OCT 077776 ALR,CLE,SLA,ALS OCT 135177 OCT 064774 OCT 077776 ALR,CLE,SLA,ARS OCT 175137 OCT 035137 OCT 077776 ALR,CLE,SLA,RAL OCT 135177 OCT 164774 OCT 077776 ALR,CLE,SLA,RAR OCT 175137 OCT 035137 OCT 077776 ALR,CLE,SLA,ERA OCT 175137 OCT 035137 OCT 077776 ALR,CLE,SLA,ELA OCT 135177 OCT 164774 OCT 077776 ALR,CLE,SLA,ALF OCT 175177 OCT 047747 OCT 077776 SKP ERA,CLE,SLA,ALS OCT 135455 OCT 135454 OCT 077776 ERA,CLE,SLA,ARS OCT 173543 OCT 176730 OCT 000002 ERA,CLE,SLA,RAL OCT 137565 OCT 137565 OCT 077776 ERA,CLE,SLA,RAR OCT 057333 OCT 153666 OCT 000002 ERA,CLE,SLA,ALR OCT 157433 OCT 057432 OCT 000002 ERA,CLE,SLA,ELA OCT 154733 OCT 154732 OCT 100002 ERA,CLE,SLA,ALF OCT 154733 OCT 147336 OCT 000002 ELA,CLE,SLA,ALS OCT 135755 OCT 067666 OCT 000002 ELA,CLE,SLA,ARS OCT 135755 OCT 035755 OCT 000002 ELA,CLE,SLA,RAL OCT 135755 OCT 167666 OCT 000002 ELA,CLE,SLA,RAR OCT 157553 OCT 157553 OCT 000002 ELA,CLE,SLA,ERA OCT 137553 OCT 037553 OCT 100002 SKP ELA,CLE,SLA,ALR OCT 177553 OCT 076656 OCT 000002 ELA,CLE,SLA,ALF OCT 054321 OCT 015073 OCT 000002 ALF,CLE,SLA,ALS OCT 054321 OCT 115052 OCT 000002 ALF,CLE,SLA,ARS OCT 054321 OCT 143212 OCT 000002 ALF,CLE,SLA,RAL OCT 054321 OCT 015053 OCT 000002 ALF,CLE,SLA,RAR OCT 054321 OCT 143212 OCT 000002 ALF,CLE,SLA,ALR OCT 054321 OCT 015052 OCT 000002 ALF,CLE,SLA,ELA OCT 054321 OCT 015052 OCT 100002 ALF,CLE,SLA,ERA OCT 054321 OCT 043212 OCT 100002 SKP ALR OCT 073107 OCT 066216 OCT 000000 ALR,ALR OCT 066216 OCT 031070 OCT 100002 ALR,CLE OCT 104670 OCT 011560 OCT 000002 CLE,ALR OCT 011560 OCT 023340 OCT 000002 SLA,ALR OCT 130661 OCT 061542 OCT 100002 ALR,SLA OCT 130661 OCT 061542 OCT 077774 SLA,ALR OCT 061542 OCT 043304 OCT 177776 ALR,SLA,ALR OCT 163153 OCT 014654 OCT 077774 ALR,CLE,ALR OCT 127717 OCT 037474 OCT 000002 CLE,SLA,ALR OCT 037474 OCT 077170 OCT 077776 ALR,CLE,SLA OCT 163153 OCT 046326 OCT 077774 ALR,CLE,SLA,ALR OCT 046326 OCT 031530 OCT 077776 CLE,SLA,ALR OCT 163153 OCT 046326 OCT 000002 SKP ORG 11777B ************************************************************* * * TEST SECTION FOR EAUSH AND MOP(EXCEPT JL*, WHICH * RESIDES ON ANOTHER PAGE. * * THIS IS A TABLE DRIVEN TEST, WITH TABLE ENTRIES * DEFINED IN A COMMENT AREA PRECEDING THE TABLE * ************************************************************* TST04 CLA STA EANOP STORES NOP INTO 2ND INS WORD LDA MOPNU LOADS NUMBER OF MOP TESTS STA TEMOP STORE TO COUNTER LOCATION LDA EAUNU LOADS # EAU TESTS STA TEAUN STORES TO TEMPORARY LDA TABL2 LOADS TABLE ADDRESS STA TEAPT STORES TO TEMP POINTER FOR INCING JMP LOOPE EXECUTE EAUSH INSTRUCTIONS FIRST LOOPM LDA TEAPT,I LOADS ADDRESS STA EANOP STORES TO SECOND WORD OF INS ISZ TEAPT NO ROLLOVER POSSIBLE LOOPE LDA TEAPT,I LOADS INSTRUCTION STA EAINS STORES TO INSTRUCTION LOCATION ISZ TEAPT NO ROLLOVER POSSIBLE LDA TEAPT LOAD POINTER VALUE STA TEOV STORE FOR LATER USE LDA A,I LOADS E,OV NEEDS SLA CHECK OV NEED JMP OTO1E CLO JMP CHEE JUMP TO CHECK E OTO1E STO CHEE SSA CHECK E NEEDS JMP ETO1E CLE JMP GOE ETO1E CCE GOE ISZ TEAPT NO ROLLOVER POSSIBLE LDB TEAPT,I LOAD B ISZ TEAPT NO ROLLOVER POSSIBLE LDA TEAPT,I LOAD A ISZ TEAPT NO ROLLOVER POSSIBLE EAINS NOP FIRST INSTRUCTION WORD EANOP NOP SECOND INSTRUCTION WORD SKP ************************************************************* * INSTRUCTION HAS BEEN EXECUTED, NOW CHECK THE RESULTS ************************************************************* CPA TEAPT,I CHECK A RSS JSB CPUER,I A IS NOT CORRECT ISZ TEAPT NO ROLLOVER POSSIBLE CPB TEAPT,I CHECK B RSS JSB CPUER,I B NOT CORRECT ISZ TEAPT NO ROLLOVER POSSIBLE LDA TEOV,I LOADS EXPECTED E AND OV ALF,ALF GET BITS TO RIGHT LOCATION SLA CHECK OV RESULT JMP OEQ1 SOC CHECK IF 0 IS 0 AS NEEDED JSB CPUER,I OV IS 1 NOT 0 CHEKE SSA CHECK E NEEDED JMP EEQ1 SEZ CHECK IF E IS 0 JSB CPUER,I E IS 1,NOT A 0 JMP NEW OEQ1 SOS CHECK OV JSB CPUER,I OV IS 0 NOT A 1 JMP CHEKE EEQ1 SEZ,RSS CHECK E VALUE JSB CPUER,I E WAS 0 NOT A 1 NEW ISZ TEAUN INCREMENT NO TESTS REMAINING JMP LOOPE MORE EAU TESTS TO DO CCA A=-1 STA TEAUN ISZ TEMOP INCREMENT NUMBER OF MOPS TO DO JMP LOOPM MOREMOPS JMP NAXT SKP ************************************************************* * THIS TABLE CONTAINS VALUES USED DURING THE TEST * BY THE EAUSH/MOP ROUTINE ************************************************************* EAUNU DEC -96 NUMBER OF TESTS IN EAU TEAUN NOP TEMPORARY COUNTER TABL2 DEF TAB2 TABLE ADDRESS TEAPT NOP TEMPORARY MOPNU DEC -35 NUMBER OF TESTS IN (MOP)+1 TEMOP NOP TEMPORARY COUNTER TEOV NOP TEMPORARY STORAGE MONE DEC 1 ONE DL1 OCT 125252 OCT 052525 DL2 OCT 077777 OCT 107070 DST1 NOP NOP SPC 1 ************************************************************* * THE FOLLOWING TABLE CONTAINS THE SETUP, INSTRUCTION * AND RESULTS FOR ALL TESTS OF EAUSH AND MOP(EXCEPT * JL* AND CERTAIN TESTS OF DIV WHERE THE RESULT IS * INDETERMINATE,SUCH AS DIVIDE BY 0...SEE LATER CODE * FOR THIS CASE ************************************************************* * TABLE SETUP: * * * WORD 0(MOP TESTS ONLY): CONTAINS ADDRESS OF WORD USED * IN OPERATION * WORD 1: CONATINS OP CODE OF INSTRUCTION TO BE EXECUTED * WORD 2: CONTAINS THE E AND OV SETUP AND RESULTS,AS FOLLOWS: * BIT 15: E SETUP PRIOR TO TEST * BIT 8: OV RESULTS AFTER TEST * BIT 7: E RESULTS AFTER TEST * BIT 0: OV SETUP PRIOR TO TEST * BITS 14-9,6-1: UNUSED * WORD 3: CONTENTS TO LOAD INTO B PRIOR TO TEST * WORD 4: CONTENTS TO LOAD INTO A PRIOR TO TEST * WORD 5: RESULTS IN A AFTER TEST * WORD 6: RESULTS IN B AFTER TEST SKP TAB2 RRR 1 RRR AREA OCT 100200 OCT 054273 OCT 161632 OCT 170715 OCT 026135 RRR 2 OCT 100200 OCT 161632 OCT 054273 OCT 113056 OCT 174346 RRR 3 OCT 100200 OCT 054273 OCT 161632 OCT 076163 OCT 045427 RRR 4 OCT 100200 OCT 161632 OCT 054273 OCT 122613 OCT 137071 RRR 5 OCT 100200 OCT 054273 OCT 161632 OCT 157434 OCT 151305 RRR 6 OCT 100200 OCT 161632 OCT 054273 OCT 064542 OCT 167616 RRR 7 OCT 100200 OCT 054273 OCT 161632 OCT 073707 OCT 032261 RRR 8 OCT 100200 OCT 054273 OCT 161632 OCT 135743 OCT 115130 RRR 9 OCT 100200 OCT 032261 OCT 073707 OCT 054273 OCT 161632 SKP RRR 10 OCT 100200 OCT 167616 OCT 064542 OCT 161632 OCT 054273 RRR 11 OCT 100200 OCT 151305 OCT 157434 OCT 054273 OCT 161632 RRR 12 OCT 100200 OCT 137071 OCT 122613 OCT 161632 OCT 054273 RRR 13 OCT 100200 OCT 045427 OCT 076163 OCT 054273 OCT 161632 RRR 14 OCT 100200 OCT 174346 OCT 113056 OCT 161632 OCT 054273 RRR 15 OCT 100200 OCT 026135 OCT 170715 OCT 054273 OCT 161632 RRR 16 OCT 100200 OCT 054273 OCT 161632 OCT 054273 OCT 161632 SKP RRL 15 OCT 100200 OCT 161632 OCT 054273 OCT 170715 OCT 026135 RRL 14 OCT 100200 OCT 054273 OCT 161632 OCT 113056 OCT 174346 RRL 13 OCT 100200 OCT 161632 OCT 054273 OCT 076163 OCT 045427 RRL 12 OCT 100200 OCT 054273 OCT 161632 OCT 122613 OCT 137071 RRL 11 OCT 100200 OCT 161632 OCT 054273 OCT 157434 OCT 151305 RRL 10 OCT 100200 OCT 054273 OCT 161632 OCT 064542 OCT 167616 SKP RRL 9 OCT 100200 OCT 161632 OCT 054273 OCT 073707 OCT 032261 RRL 8 OCT 100200 OCT 054273 OCT 161632 OCT 115130 OCT 135743 RRL 7 OCT 100200 OCT 032261 OCT 073707 OCT 161632 OCT 054273 RRL 6 OCT 100200 OCT 167616 OCT 064542 OCT 054273 OCT 161632 RRL 5 OCT 100200 OCT 151305 OCT 157434 OCT 161632 OCT 054273 RRL 4 OCT 100200 OCT 137071 OCT 122613 OCT 054273 OCT 161632 RRL 3 OCT 100200 OCT 045427 OCT 076163 OCT 161632 OCT 054273 RRL 2 OCT 100200 OCT 174346 OCT 113056 OCT 054273 OCT 161632 RRL 1 OCT 100200 OCT 026135 OCT 170715 OCT 161632 OCT 054273 RRL 16 OCT 100200 OCT 054273 OCT 161632 OCT 054273 OCT 161632 SKP LSR 1 OCT 100200 OCT 054273 OCT 161632 OCT 170715 OCT 026135 LSR 2 OCT 100200 OCT 161632 OCT 054273 OCT 113056 OCT 034346 LSR 3 OCT 100200 OCT 054273 OCT 161632 OCT 076163 OCT 005427 LSR 4 OCT 100200 OCT 161632 OCT 054273 OCT 122613 OCT 007071 LSR 5 OCT 100200 OCT 054273 OCT 161632 OCT 157434 OCT 001305 LSR 6 OCT 100200 OCT 161632 OCT 054273 OCT 064542 OCT 001616 LSR 7 OCT 100200 OCT 054273 OCT 161632 OCT 073707 OCT 000261 LSR 8 OCT 100200 OCT 161632 OCT 054273 OCT 115130 OCT 000343 SKP LSR 9 OCT 100200 OCT 000261 OCT 073707 OCT 054273 OCT 000000 LSR 10 OCT 100200 OCT 001616 OCT 064542 OCT 161632 OCT 000000 LSR 11 OCT 100200 OCT 001305 OCT 157434 OCT 054273 OCT 000000 LSR 12 OCT 100200 OCT 007071 OCT 122613 OCT 161632 OCT 000000 LSR 13 OCT 100200 OCT 005427 OCT 076163 OCT 054273 OCT 000000 LSR 14 OCT 100200 OCT 034346 OCT 113056 OCT 161632 OCT 000000 LSR 15 OCT 100200 OCT 026135 OCT 170715 OCT 054273 OCT 000000 LSR 16 OCT 100200 OCT 054273 OCT 161632 OCT 054273 OCT 000000 SKP ASR 1 OCT 100201 OCT 054273 OCT 161632 OCT 170715 OCT 026135 ASR 2 OCT 100201 OCT 161632 OCT 054273 OCT 113056 OCT 174346 ASR 3 OCT 100201 OCT 054273 OCT 161632 OCT 076163 OCT 005427 ASR 4 OCT 100201 OCT 161632 OCT 054273 OCT 122613 OCT 177071 ASR 5 OCT 100201 OCT 054273 OCT 161632 OCT 157434 OCT 001305 ASR 6 OCT 100201 OCT 161632 OCT 054273 OCT 064542 OCT 177616 ASR 7 OCT 100201 OCT 054273 OCT 161632 OCT 073707 OCT 000261 ASR 8 OCT 100201 OCT 161632 OCT 054273 OCT 115130 OCT 177743 SKP ASR 9 OCT 100201 OCT 000261 OCT 073707 OCT 054273 OCT 000000 ASR 10 OCT 100201 OCT 177616 OCT 064542 OCT 161632 OCT 177777 ASR 11 OCT 100201 OCT 001305 OCT 157434 OCT 054273 OCT 000000 ASR 12 OCT 100201 OCT 177071 OCT 122613 OCT 161632 OCT 177777 ASR 13 OCT 100201 OCT 005427 OCT 076163 OCT 054273 OCT 000000 ASR 14 OCT 100201 OCT 174346 OCT 113056 OCT 161632 OCT 177777 ASR 15 OCT 100201 OCT 026135 OCT 170715 OCT 054273 OCT 000000 ASR 16 OCT 100201 OCT 054273 OCT 161632 OCT 054273 OCT 000000 SKP LSL 15 OCT 100601 OCT 000000 OCT 054273 OCT 100000 OCT 026135 LSL 14 OCT 000401 OCT 054273 OCT 161632 OCT 100000 OCT 174346 LSL 13 OCT 000000 OCT 161632 OCT 054273 OCT 060000 OCT 045427 LSL 12 OCT 100200 OCT 054273 OCT 161632 OCT 120000 OCT 137071 LSL 11 OCT 000000 OCT 161632 OCT 054273 OCT 154000 OCT 151305 LSL 10 OCT 100601 OCT 054273 OCT 161632 OCT 064000 OCT 167616 SKP LSL 9 OCT 000401 OCT 161632 OCT 054273 OCT 073000 OCT 032261 LSL 8 OCT 100200 OCT 054273 OCT 161632 OCT 115000 OCT 135743 LSL 7 OCT 000000 OCT 032261 OCT 073000 OCT 000000 OCT 054273 LSL 6 OCT 100200 OCT 167616 OCT 064000 OCT 000000 OCT 161632 LSL 5 OCT 100601 OCT 151305 OCT 154000 OCT 000000 OCT 054273 LSL 4 OCT 000401 OCT 137071 OCT 120000 OCT 000000 OCT 161632 LSL 3 OCT 000000 OCT 045427 OCT 060000 OCT 000000 OCT 054273 LSL 2 OCT 100200 OCT 174346 OCT 100000 OCT 000000 OCT 161632 LSL 1 OCT 100601 OCT 026135 OCT 100000 OCT 000000 OCT 054273 LSL 16 OCT 000401 OCT 161632 OCT 054273 OCT 000000 OCT 054273 SKP ASL 15 OCT 100600 OCT 161632 OCT 054273 OCT 100000 OCT 126135 ASL 14 OCT 100600 OCT 054273 OCT 161632 OCT 100000 OCT 074346 ASL 13 OCT 100600 OCT 161632 OCT 054273 OCT 060000 OCT 145427 ASL 12 OCT 100600 OCT 054273 OCT 161632 OCT 120000 OCT 037071 ASL 11 OCT 100600 OCT 161632 OCT 054273 OCT 154000 OCT 151305 ASL 10 OCT 100600 OCT 054273 OCT 161632 OCT 064000 OCT 067616 SKP ASL 9 OCT 100600 OCT 161632 OCT 054273 OCT 073000 OCT 132261 ASL 8 OCT 100600 OCT 054273 OCT 161632 OCT 115000 OCT 035743 ASL 7 OCT 100600 OCT 132261 OCT 073000 OCT 000000 OCT 154273 ASL 6 OCT 100600 OCT 067616 OCT 064000 OCT 000000 OCT 061632 ASL 5 OCT 100600 OCT 151305 OCT 154000 OCT 000000 OCT 154273 ASL 4 OCT 100600 OCT 037071 OCT 120000 OCT 000000 OCT 061632 ASL 3 OCT 100600 OCT 145427 OCT 060000 OCT 000000 OCT 154273 ASL 2 OCT 100600 OCT 074346 OCT 100000 OCT 000000 OCT 061632 ASL 1 OCT 100600 OCT 126135 OCT 100000 OCT 000000 OCT 154273 ASL 16 OCT 100600 OCT 161632 OCT 054273 OCT 000000 OCT 154273 SKP ******************** * TEST MOPS * ******************** DEF DL1 OCT 104200 DLD OP OCT 000000 OCT 143221 OCT 152343 OCT 125252 OCT 052525 DEF DST1 OCT 104400 DST OP OCT 000000 OCT 052525 OCT 125252 OCT 125252 OCT 052525 DEF DST1 OCT 104200 DLD OP, TO CHECK DST OCT 000000 OCT 134562 OCT 123212 OCT 125252 OCT 052525 DEF DL2 OCT 104200 DLD OP OCT 100601 E AND OV STAY OCT 1 OCT 126453 OCT 163542 OCT 077777 OCT 107070 DEF DST1 OCT 104400 DST OP OCT 100601 OCT 107070 OCT 077777 OCT 077777 OCT 107070 DEF DST1 OCT 104200 DLD OP, TO CHECK DST OCT 100601 OCT 123432 OCT 154321 OCT 077777 OCT 107070 * ONE ATTEMPT AT INDIRECTS FOR MOP WILL TEST.. * SAME LOGIC USED FOR INDIRECTS DEF INDLD,I OCT 104200 DLD OCT 000000 OCT 000000 OCT 000000 OCT 177777 OCT 052525 DEF MONE OCT 100200 (MPY) OCT 100201 OCT 177777 OCT 000000 OCT 000000 OCT 000000 DEF DL2 OCT 100200 MPY OP OCT 100201 OCT 177777 OCT 000000 OCT 000000 OCT 000000 DEF DL3I OCT 100200 MPY OP OCT 100201 OCT 177777 OCT 000000 OCT 000000 OCT 000000 SKP DEF MONE OCT 100200 MPY OP OCT 100201 OCT 000000 OCT 177777 OCT 177777 OCT 177777 DEF DL2 OCT 100200 MPY OP OCT 100201 OCT 177777 OCT 125252 OCT 052526 OCT 152525 DEF DL2 OCT 100200 MPY OP OCT 100201 OCT 152525 OCT 052525 OCT 025253 OCT 025252 DEF DL2 OCT 100200 MPY OP OCT 100201 OCT 025252 OCT 107070 OCT 070710 OCT 143434 DEF DL2 OCT 100200 MPY OP OCT 100201 OCT 143434 OCT 070707 OCT 007071 OCT 034343 DEF DL3I OCT 100200 MPY OP OCT 100201 OCT 034343 OCT 177777 OCT 000001 OCT 000000 DEF DL3I OCT 100200 MPY OP OCT 100201 OCT 000000 OCT 125252 OCT 052526 OCT 000000 DEF DL3I OCT 100200 MPY OP OCT 100201 OCT 000000 OCT 052525 OCT 125253 OCT 177777 DEF DL3I OCT 100200 MPY OP OCT 100201 OCT 177777 OCT 070707 OCT 107071 OCT 177777 DEF MNEG OCT 100200 MPY OP OCT 100201 OCT 177777 OCT 125252 OCT 000000 OCT 025253 SKP DEF MNEG OCT 100200 MPY OP OCT 100201 OCT 025253 OCT 052525 OCT 100000 OCT 152525 DEF DL1A OCT 100200 MPY OP OCT 100201 OCT 152525 OCT 052525 OCT 107071 OCT 016161 DEF DL1 OCT 100200 MPY OP OCT 100201 MU2B OCT 016161 OCT 125252 MU3A OCT 034344 OCT 016162 DEF MNEG OCT 100400 DIV OP CODE OCT 000000 OCT 000000 OCT 125252 OCT 177777 OCT 025252 DEF MNEG OCT 100400 DIV OP CODE OCT 000000 OCT 177776 OCT 125252 OCT 000002 OCT 125252 DEF DL2 OCT 100400 DIV OPCODE OCT 000000 OCT 177776 OCT 125252 OCT 177776 OCT 125250 DEF DL2 OCT 100400 DIV OP CODE OCT 000000 OCT 007777 OCT 177777 OCT 020000 OCT 017777 DEF MNEG OCT 100400 DIV OPCODE OCT 000000 OCT 007777 OCT 177777 OCT 160001 OCT 077777 DEF MNEG OCT 100400 DIV OPCODE OCT 000000 OCT 177777 OCT 160001 OCT 000000 OCT 160001 DEF MNEG OCT 100400 DIV OP CODE OCT 000000 OCT 152525 OCT 052526 OCT 052525 OCT 152526 DEF DL2 OCT 100400 DIV OPCODE OCT 000000 OCT 152525 OCT 052526 OCT 125252 OCT 000000 DEF DL2 OCT 100400 DIV OP CODE OCT 000000 OCT 000707 OCT 070707 OCT 001616 OCT 072525 DEF MNEG OCT 100400 DIV OPCODE OCT 000000 OCT 000707 OCT 070707 OCT 176162 OCT 070707 DEF MONE DIV BY 2**-15 OCT 100400 OCT 100200 OCT 177777 OCT 100000 OCT 100000 OCT 000000 SKP ************************************************************* * THIS SECTION TESTS DIV FAILING IF DIVIDE BY 0 * OR DIVIDE BY A NUMBER TOO SMALL. * RESULTS WILL BE A AND B INDETERMINATE AND * OV WILL BE SET ************************************************************* NAXT CLA,CLE CLO CCB DIV ZEROD DIVIDE BY ZERO...OVWILL BE SET SOS C JSB CPUER,I OV FAILED TO SET SEZ JSB CPUER,I E WAS INCORRECTLY SET LDA ZEROD LDB MNEG DIV MONE DIVIDE MAXIMUM NEG NUMBER BY 1(OVWILL SET) SOS C JSB CPUER,I OV FAILED TO SET SEZ JSB CPUER,I E FAILEDWAS INCORRECTLY SET BY DIVIDE FAIL CCA LDB DL2 * B-A CONTAIN MAXIMUM SIZE POSITIVE NUMBER DIV MONE DIVIDE MAXIMUM SIZE POSITIVE NUMBER BY 1(OV WILL SET) SOS C JSB CPUER,I OV FAILED TO SET ON DIVIDE FAIL SEZ JSB CPUER,I E WAS INCORRECTLY SET JMP *+1,I JUMP TO NEXT TEST DEF TSTJL NOW MOVE TO JL* TEST DL3I OCT 177777 DL1A OCT 052525 ZEROD OCT 0 MNEG OCT 100000 INDLD DEF DL3I SKP * *CPU ERROR ROUTINE. LOADS A REGISTER WITH STATUS * *AND SUB-SECTION OF CPU TEST THAT FAILED FOR * *OUTPUT TO LED'S THROUGH DISPLAY * CPERR NOP RETURN ADDRESS TO PROGRAM STA ERRA STORE A STB ERRB AND B TEMPORARILY LDA B10 NO GET PATTERN FOR CPU ERROR JSB DISP,I GO DISPLAY IT ADB CPERR CREATE BAD INSTR. ADDRESS CLA CLEAR OUT A HLT 10B LDA ERRA LDB ERRB GET A AND B AGAIN HLT 50B STOP AND DISPLAY JMP CPERR+3 NEVER LEAVE THIS AREA SPC 3 * *PROCESSOR ERROR ROUTINE * *CAUSES ADDRESS OF FAILURE IN KERNAL PLUS WHICH * *BOARD FAILED TO BE SENT TO FRONT PANEL, OR. . . . * *CAUSES LED'S TO FLASH WITH BOARD AND SUB-SECTION * *THAT FAILED * PRERR NOP ADDRESS OF FAILURE +1 STA ERRA STORE A STB ERRB AND B TEMPORARILY JSB RSTRP RESTORE TRAP CELL CLF PES RESET SENSE STC PES TURN ON PARITY SYSTEM CLC 0,C TURN OFF INTERRUPTS LDA B11 GET PATTERN FOR PROCESSOR ERROR DISPLAY ALF,ALF MOVE IT TO UPPER HALF IOR CNTR GET SUB-SECTION FAILURE ALF,ALF MOVE IT BACK JSB DISP,I GO DISPLAY IT ADB PRERR CREATE FAILING ADDRESS HLT 11B GO AND DISPLAY FRONT PANEL LDA ERRA GET A AND LDB ERRB B AGAIN HLT 51B GO DISPLAY FRONT PANEL JMP PRERR+4 NEVER LEAVE THIS AREA SKP * * *I/O ERROR HANDLING ROUTINE * IOERR NOP RETURN ADDRESS CLC 0B,C RESET I/O DEVICES INCLUDING INT. STA ERRA SAVE A STB ERRB SAVE B JSB RSTRP RESTORE TRAP CELL CLA CLEAR A TO OTA GR TURN OFF DIAGNOSE MODE JSB RSTRP RESTORE JSB ILINT TO TRAP CELL IN USE LDA JSBIL RESTORE JSB ILINT TO MPT TRAP CELL STA MTRAP LDA POINT,I GET SELECT CODE UNDER TEST ELA,CLE,ERA ALF,ALF MOVE IT TO UPPER HALF IOR B13 JSB DISP,I GO DISPLAY IT ADB IOERR CREATE BAD INSTRUCTION ADDRESS HLT 13B GO DISPLAY IT LDA ERRA YES SO RESTORE A LDB ERRB AND B HLT 53B JMP IOERR+10 NEVER LEAVE THIS AREA. HED PROCESSOR I/O FUNCTIONS UNDER TEST * *VERIFY THAT THE PROCESSOR I/O FUNCTIONS WORK * ORG 13777B TST05 CLC 0,C CLEAR I/O (INSTR. ASSUMED FUNCTIONAL) LDA B11 GET STATUS = CPU UNDER TEST OTA LEDS OUTPUT TO LEDS JSB IREGC GO CHECK PROCESSOR REGISTERS LDA B6 PUT A BINARY SIX INTO SUB-SECTION STA CNTR COUNTER STF GR DISABLE THE GLOBAL REGISTER SFC GR IS THE GLOBAL REGISTER DISABLED AND SFS GR DO SFS AND SFC WORK? JSB PROER,I NO. STF,SFS, OR SFC DIDN'T WORK SFS 0 IS THE INTERRUPT FF CLEAR SFC 0 AND DO SFS AND SFC WORK? JSB PROER,I NO. SFS OR SFC FAILED. CLF TBG CLEAR TBG FLAG SFS TBG IS THE TBG FLAG CLEAR? SFC TBG AND DO SFS AND SFC WORK? JSB PROER,I NO. FLAG NOT CLEAR OR SFS-SFC FAILURE CLA CLEAR THE INTERRUPT MASK OTA INMSK STF 0 TURN ON THE INTERRUPT SYSTEM SFC 0 IS IT ON AND DO SFS-SFC WORK? SFS 0 JSB PROER,I NO. STF, SFC, OR SFS FAILED CLF 0 DISABLE INTERRUPTS * IF INT OCCURS, CLF 0 DIDN'T WORK SO JSB ILINT STF TBG DOES TBG FLAG WORK? NOP DOES INTERRUPT OCCUR? SFC TBG DOES SFS-SFC TBG WORK? SFS TBG JSB PROER,I NO. STF, SFS, SFC FAILED ON TBG CLF TBG CAN TBG FLAG BE CLEARED AND SFS TBG DO SFS AND SFC WORK? SFC TBG JSB PROER,I NO. CLF,SFS, OR SFC FAILURE ON TBG LDA B6 SET TRAP CELL = JMP INTOK JSB JPTRP DEF INTOK STF 0 ENABLE INTERRUPTS STF TBG FORCE A TBG INTERRUPT * * (CONTINUED) * SKP NOP LET IT INTERRUPT JSB PROER,I TBG DIDN'T INT OR INT NOT ALLOWED INTOK CLF TBG INTERRUPT GOOD FROM TBG; TURN OFF JSB RSTRP RESTORE JSB ILINT TO TRAP CELL LIA CIR WAS CIR LOADED CORRECTLY? CPA PAT12 PAT12=000006 RSS YES JSB PROER,I NO LDA PAT00 TRY A MERGE; A = 177700 LDB PAT13 B = 177706 MIA CIR MERGE A WITH CIR CPA B MERGE GOOD? RSS YES JSB PROER,I NO HED TIME BASE GENERATOR TEST * * *CHECK ALL TBG FUNCTIONS * TBTST CCE INITIALIZE E = 1 LDA B6 A = TRAP CELL ADDRESS JSB JPTRP TRP06 = JMP IN10M DEF IN10M STC TBG TURN ON TBG TIM10 CLB THIS LOOP TAKES 11 MS INB CPB B11MS HAS 11 MS ELAPSED? RSS YES - SHOULD HAVE INTERRUPTED JMP *-3 NO REPEAT UNTIL TIMEOUT OR INT. CLC TBG,C NO INTERRUPT. TURN OFF TBG JSB PROER,I AND GO SHOW ERROR. IN10M SEZ,CME IS THIS THE FIRST INTERRUPT? JMP TIM10 YES - WAIT FOR SECOND INTERRUPT CLC TBG,C NO, IT IS THE SECOND. CONTINUE ADB MB9MS CHECK THAT IT IS GREATER THAN 9 MS SSB ?? JSB PROER,I NO IT WASN'T SO ERROR * DOES CLC TURN OFF TBG INTERRUPTS? JSB RSTRP RESTORE JSB ILINT TO TRAP CELL CLB WAIT FOR AN INTERRUPT ISZ B IF INTERRUPT OCCURS, GO OUT OF JMP *-1 LOOP TO ILLEGAL INT. CLF 0 NO INTERRUPT. CLF 0 HOLD OFF INT.? STC TBG TURN ON TBG ISZ B WAIT FOR AN INTERRUPT THAT SHOULDN'T JMP *-1 OCCUR. IF IT DOES, JSB ILINT LDA B2 NO INTERRUPT. CHECK INTERRUPT MASK OTA INMSK TO MASK TBG INT. STF 0 ENABLE INTERRUPTS ISZ B WAIT FOR AN INTERRUPT THAT SHOULDN'T JMP *-1 OCCUR. IF IT DOES, JSB ILINT CLA NO INT. CLEAR INMSK OTA INMSK CLC 0,C CLEAR I/O ISZ B CLC 0,C TURN OFF INTERRUPTS? JMP *-1 IF INT. OCCURS, JSB ILINT CLC TBG,C TURN OFF TBG SKP * * CHECK THAT STC4 HOLDS OFF INTERRUPTS * STF 0B TURN ON INTERRUPTS CLC 4B TURN OFF INTERRUPTS (2 & 3) STC TBG TURN ON TBG SFS 4B IS POWER GOING DOWN? JMP 4B YES - RESTART THE PROGRAM ISZ B WAIT FOR AN INT. IF INT. OCCURS JMP *-3 JSB ILINT. CLC 4 DIDN'T DISABLE INT. LDA B6 NO INT. - SET TRAP CELL JSB JPTRP TRAP CELL 6 = JMP TIM11 DEF TIM11 STC 4 TURN ON INTERRUPTS ISZ B WAIT FOR INTERRUPT JMP *-1 JSB PROER,I NO INTERRUPT SO ERROR (STC 4 DIDN'T WORK) TIM11 CLC TBG,C TURN OFF TBG CLC 0,C AND WORLD JSB RSTRP RESTORE THE TRAP CELL * * * *TEST A JSB IN A TRAP CELL * JSBTR LDA B6 GET TBG SELECT CODE JSB JSTRP TBG TRAP CELL = JSB INTJS DEF INTJS CLA CLEAR TEMP0 STA TEMP0 STF TBG FORCE TBG INTERRUPT STF 0 ENABLE INTERRUPTS ISZ TEMP0 ONE ISZ SHOULD EXECUTE, THEN INTERRUPT INTJ. ISZ TEMP0 THIS SHOULD NOT BE EXECUTED JSB PROER,I NO INTERRUPT INTJS NOP TBG INTERRUPTED CLC 0,C DISABLE INTERRUPTS LDB TEMP0 CHECK HOW MANY ISZ'S WERE EXECUTED CPB B1 ONLY ONE? RSS YES JSB PROER,I TOO MANY ISZ'S JSB RSTRP RESTORE TRAP CELL JSB ILINT LDB INTJS GET SUBROUTINE RETURN ADDRESS CPB INJS. PROPER RETURN ADDRESS? (SEE BELOW) JMP *+3 YES -- GO ON JSB PROER,I NO ERROR INJS. DEF INTJ. CORRECT RETURN ADDRESS STF 0 ENABLE INTERRUPTS HED UNIMPLEMENTED INSTRUCTION TEST * * *TEST THE UNIMPLEMENTED INSTRUCTION TRAP * UITST LDA B10 A = TRAP CELL ADDRESS STA CNTR STORE THIS IN SUB-SECTION COUNTER JSB JSTRP TRP03 = JSB UIINT (ROUTINE IN BP) DEF UIINT CLB CLEAR TEMP7 STB TEMP7 UI OCT 105100 TRY TO EXECUTE UNIMPLEMENTED CODE OCT 104700 OCT 104000 NOTE: THESE SIX CODES CHECK ALL OCT 105600 UNIMPLEMENTED INSTRUCTION OCT 101300 DECODING LOGIC ON THE CPU CHIP OCT 101500 OCT 104100 OCT 104300 OCT 100300 OCT 101200 OCT 101400 OCT 101600 OCT 101700 OCT 100500 OCT 104500 OCT 100700 NOP JSB RSTRP RESTORE JSB ILINT TO TRAP CELL LDA TEMP7 GET TEMP7 CONTENTS CPA B20 WERE 20B INTERRUPTS PROCESSED? JMP MPTST YES - GO TEST MEMORY PROTECT JSB PROER,I NO * * *UNIMPLEMENTED INSTRUCTION TRAP WORKS CORRECTLY * HED MEMORY PROTECT TESTS * * *THE MEMORY PROTECT TEST * * *TEST THAT A HALT IS NOT ALLOWED BY MPT. * MPTST CLB FENCE WILL BE ZERO. LDA B7 LOAD A BINARY SEVEN AND STA CNTR STORE IN SUB-SECTION COUNTER STF 0 ENABLE INTERRUPTS LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB CHKIN DEF CHKIN JSB INTMP INITIALIZE MPT. LDA EA001 GET EXPECTED VIOLATION ADDRESS. STA EXPVR SAVE IT. STC5 STC MPT TURN ON MPT. NOP SHOULD NOT INTERRUPT HERE. TH001 HLT 03 MPT SHOULD NOT ALLOW HALT HERE. RSS FLASH LEDS IF NO MPT INT AND NO BREAK JMP MPT01 INTERRUPT GOOD. DO NEXT TEST FLASH LDA B7 GET CURRENT STATUS = MPT HANGING UP ALF,ALF MOVE IT TO UPPER HALF IOR B11 CPU BOARD LDB A PUT IT IN B JMP DISP5,I SKP * * *INSURE AN I/O INSTRUCTION IS NOT ALLOWED. * MPT01 LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB CHKIN DEF CHKIN JSB INTMP GO INITIALIZE MPT. LDA EA003 GET EXPECTED VIOLATION ADDRESS. STA EXPVR SAVE IT. CLB CLEAR B FOR TEST. STC MPT TURN ON MPT TH003 LIB CIR INSTRUCTION SHOULD CAUSE VIOLATION HLT 03 SHOULD NEVER GET HERE. SZB,RSS WAS B-REG ALTERED? JMP MPT02 NO - CONTINUE TESTING. JSB PROER,I LIB WAS ALLOWED SKP * * *INSURE NO VIOLATION OCCURS WITHOUT A STC 7 * AND VERIFY SELECT CODE 7 IS DECODED PROPERLY * MPT02 CLB FENCE WILL BE ZERO. LDA BMPT A = MPT S/C JSB JPTRP TRAP CELL = JMP ERR02 DEF ERR02 JSB INTMP INITIALIZE MPT. CLA CLEAR A LIA CIR NO INTERRUPT - MPT OFF, A = NON-ZERO SZA,RSS DID LIA CIR EXECUTE? JSB PROER,I NO LDA LISCC GET LIA SC,C INSTRUCTION STA INLIN PUT IN LINE LDB PAT24 SET UP COMPLETION INDICATOR. INLIN LIA SC,C EXECUTE TO VERIFY NO S/C 7 WAS DECODED CPA EA003 WAS THE VIOLATION REGISTER READ? JSB PROER,I YES - S/C 7 DECODED, INLIN = BAD S/C ISZ INLIN INCREMENT SELECT CODE CPB INLIN HAVE ALL S/C'S BEEN CHECKED? JMP MPT03 YES - GO TO NEXT TEST LDA LIVIO NO - IS S/C 7 THE NEXT S/C? CPA INLIN ISZ INLIN YES - INCREMENT THE S/C AGAIN JMP INLIN NO - TEST IT ERR02 JSB PROER,I MPT INTERRUPT WITH MPT OFF SKP * * *TEST ALL NON-VIOLATING INSTRUCTIONS * MPT03 LDB B5 FENCE VALUE. LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB ERR03 DEF ERR03 JSB INTMP INITIALIZE MPT. STC MPT TURN ON MPT. * * *TEST MEMORY REFERENCE INSTRUCTIONS * IOR B NO INTERRUPT SHOULD OCCUR ADA B UNTIL HLT 03 AT THE END OF ADB A THIS LIST OF NON-VIOLATING AND B INSTRUCTIONS. CPA A CPB B CLA ISZ A CLB ISZ B LDB B LDB A STA B STB A XOR B * * *TEST SHIFT-ROTATE FUNCTIONS * ALS,ALS NOP BLS,BLS ARS,ARS BRS,BRS RAL,RAL RBL,RBL RAR,RAR RBR,RBR ALR,ALR BLR,BLR ERA,ERA ERB,ERB ELA,ELA ELB,ELB ALF,ALF BLF,BLF SKP * * *TEST ALTER-SKIP FUNCTIONS * CMA B7000 CMB CME CLE CCE INA INB CCA CCB RSS NOP SEZ SLA SLB SSA SSB SZA SZB * * *TEST LEGAL I/O INSTRUCTIONS * CLO SOS STO SOC LIA 1 LIB 1 MIA 1 MIB 1 STC 1 CLC 1 * * *TEST EAU INSTRUCTIONS * DIV B5 DLD SAVEA MPY B5 ASL 5 ASR 5 LSL 5 LSR 5 RRL 5 RRR 5 SKP * * *TEST JSB 0 AND JSB 1 * JSBCK CLA FENCE = 5 STA MTRAP NOP MPT TRAP CELL. HLT 03 FORCE INTERRUPT. TURN MPT OFF. LDB JARTN SET UP RETURN IN CASE OF ERROR. LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB ERR03 DEF ERR03 STC MPT TURN ON MPT JSB A SHOULD RETURN TO NEXT INST. CLA STA MTRAP CLEAR TRAP AND HLT 03 FORCE INTERRUPT. TURN OFF MPT LDA JBRTN SET UP STA TRP02 RETURN LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB ERR03 DEF ERR03 STC MPT TURN ON MPT JSB B SHOULD RETURN TO NEXT INST. CLA CLEAR MPT STA MTRAP TRAP CELL LDA TRP04 RESTORE START POINTER TO 2 HLT 03 SHUT OFF MPT STA TRP02 JMP MPT04 CONTINUE WITH NEXT TEST. ERR03 NOP LIA VIOLA GET VIOLATION ADDRESS. JSB PROER,I * * SKP * * *TEST ALL VIOLATING INSTRUCTIONS * MPT04 LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB CHKIN DEF CHKIN STA SPTST SPECIAL TEST MARKER. LDB B140 FENCE REGISTER WILL EQUAL 140 JSB INTMP INITIALIZE MPT. LDA IPNTR GET INSTRUCTION LIST POINTER. STA INPNT SAVE IT. LDA HLT03 PUT STA 100B HALTS IN STA 101B VIOLATED MEMORY. CLF GR ENABLE GLOBAL REGISTER VILOP STF 0 TURN ON INTERRUPT SYSTEM. LDA INPNT,I GET AN INSTRUCTION. CPA MIN1 END OF LIST? JMP CLSPT YES - GO CLEAR SPTST STA THT10 NO - PUT INSTRUCTION IN LINE LDA EXA01 EXPECTED VIOLATION ADDRESS. STA EXPVR SAVE IT. STC MPT TURN ON MPT. THT10 NOP VIOLATION SHOULD OCCUR HERE. OCT 100 CONSTANT IF NEEDED BY INST. HLT 03 FORCE INTERRUPT IF NONE OCCURRED NOP MOVLT ISZ INPNT MOVE INSTRUCTION POINTER. LDB 100B HAS 100 BEEN ALTERED? CPB HLT03 RSS NO JSB PROER,I YES LDB 101B HAS 101 BEEN ALTERED? CPB HLT03 RSS NO JSB PROER,I YES SFC GR FLAG SHOULD STILL BE CLEAR JSB PROER,I JMP VILOP TEST MORE INSTRUCTIONS. CLSPT CLA CLEAR SPECIAL TEST INDICATOR STA SPTST STF GR TURN OFF GLOBAL REGISTER SKP * * *TRY TO STORE AT AND BELOW FENCE * MPT05 LDA HLT03 ESTABLISH LOCATION TO BE TESTED STA 100B FOR TEST COMPARISON. LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB CHKIN DEF CHKIN LDB B101 FENCE WILL BE SET TO 101 JSB INTMP INITIALIZE MPT. LDA EA002 GET EXPECTED VIOLATION ADDRESS. STA EXPVR SAVE IT. LDB PAT02 GET A PATTERN FOR THE B-REGISTER STC MPT TURN ON MPT. STB 101B NO VIOLATION SHOULD OCCUR HERE. TH002 STB 100B VIOLATION OCCURS HERE. HLT 03 IF NO INT., MPT FENCE FAILED LDB 100B GET 100 DATA CPB HLT03 DID STORE CHANGE ADDRESS 100 DATA? JMP MPT06 NO! GO DO NEXT TEST LDA EA002 YES! GET STB LOCATION. JSB PROER,I STORE BELOW FENCE WAS ALLOWED SKP * * *STORE AT AND BELOW FENCE. THEN ROTATE FENCE * REGISTER BITS AND REPEAT UNTIL ALL BITS HAVE * BEEN CHECKED. * MPT06 CLC 0,C CLEAR THE I/O SYSTEM LDA B11 GET FIRST ADDRESS FOR THE FENCE STF 0 ENABLE INTERRUPTS CLB CLEAR TEMP5 STB TEMP5 M06.1 RAL ROTATE BITS LEFT ONE CPA B11 HAVE ALL PATTERNS BEEN CHECKED? JMP MPT07 YES STA TEMP1 SAVE THE PATTERN IOR PAT31 ADD BIT 12 TO PATTERN STA TEMP3 SAVE THE ACTUAL PATTERN FOR FENCE AND PAT15 MASK OFF BIT 15 LDB PAT02 B = 125252 STB A,I TRY TO WRITE AT THIS ADDRESS LDB A,I DID IT WRITE? (IS MEMORY THERE?) STB TEMP5 NO - REMEMBER A STORE AT FENCE WON'T WORK OTA FENCE LOAD THE FENCE REGISTER LDA BMPT A = MPT SELECT CODE JSB JPTRP TRAP CELL = JMP M06.2 DEF M06.2 LDA TEMP3 GET THE FENCE ADDRESS AND PAT15 MASK OFF BIT 15 CCB DECREMENT THE ADDRESS ADA B A = FENCE-1 STA TEMP2 SAVE FENCE-1 IN TEMP2 LDB A,I GET DATA FROM ADDRESS STB TEMP0 SAVE THE DATA CMB COMPLEMENT THE DATA * * *TRY TO STORE BELOW THE FENCE AT FENCE-1. * THIS SHOULD CAUSE A MEMORY PROTECT VIOLATION * INTERRUPT. * STC MPT TURN ON MEMORY PROTECT STBAI STB A,I TRY TO STORE AT FENCE-1 JSB PROER,I NO MPT INTERRUPT OCCURRED M06.2 JSB RSTRP RESTORE JSB ILINT TO TRAP CELL LDB A,I GET THE DATA AT THE ADDRESS CPB TEMP0 WAS IT ALTERRED? RSS NO JSB PROER,I YES - IT SHOULD NOT HAVE BEEN LIB VIOLA,C GET VIOLATION REGISTER CPB STBAD IS IT EQUAL TO STBAI'S ADDRESS? RSS YES JSB PROER,I NO SKP * * *TRY STORING AT THE FENCE. NO VIOLATION SHOULD OCCUR. * TRY TO EXECUTE AN I/O INSTRUCTION. A VIOLATION SHOULD * BE DETECTED. * LDA BMPT A = MPT SELECT CODE JSB JPTRP TRAP CELL = JMP M06.3 DEF M06.3 LDA TEMP2 GET THE FENCE ADDRESS-1 INA A = FENCE LDB A,I B = DATA AT FENCE ADDRESS CMB COMPLEMENT DATA STB TEMP4 SAVE DATA STC MPT TURN ON MEMORY PROTECT STB A,I TRY TO STORE AT FENCE IOVIO STF TBG TRY TO EXECUTE AN I/O INSTRUCTION LDA TEMP2 NO VIOLATION FROM I/O INSTRUCTION - STB A,I FORCE A VIOLATION JSB PROER,I STILL NO VIOLATION M06.3 LIB VIOLA,C GET VIOLATION REGISTER CPB IOVAD WAS VIOLATION FROM IOVIO? RSS YES JSB PROER,I NO - B = VIOLATION INSTRUCTION SFC TBG WAS STF TBG ALLOWED? JSB PROER,I YES LDB TEMP5 SHOULD A STORE AT FENCE HAVE WORKED? CPB PAT02 RSS JMP RESTR NO - DON'T CHECK THE FENCE DATA LDB A,I B = DATA FOR FENCE ADDRESS LOCATION CPB TEMP4 WAS THE STORE AT FENCE ALLOWED? RSS YES JSB PROER,I NO CMB B = ORIGINAL FENCE ADDRESS DATA STB A,I RESTORE DATA TO FENCE ADDRESS LOCATION RESTR LDA TEMP1 GET CURRENT FENCE PATTERN JSB RSTRP RESTORE JSB ILINT TO TRAP CELL JMP M06.1 TEST THE NEXT PATTERN SKP * * *THIS SECTION TESTS THE VIOLATION AND FENCE * REGISTERS AND THE VIOLATION LOGIC * MPT07 LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB CHKIN DEF CHKIN LDA MP08D SET UP INITIAL FENCE STA FENVA REGISTER SETTING. TLOOP LDA FENVA GET PRESENT FENCE. STA TEMP4 SAVE FENCE VALUE ADA LECOD ADD LENGTH OF TEST MODULE. IOR B7 OR WITH BITS 0,1,2 CPA EOM END OF MEMORY? JMP M08AD,I YES - GO TO NEXT TEST, MPT08 LDB NLNCD NO! MOVE DATA OUT OF AREA STB MCNTR SAVE MOVE COUNT IN WORDS. LDB BUFAD GET ADDRESS OF SAVE BUFFER STB BUFPT SAVE IT. LDA TEMP4 JSB MOVE MOVE DATA BLOCK. LDA STCOD MOVE TEST MODULE IN AREA LDB FENVA JUST REMOVED. STB BUFPT SAVE MODULE ADDRESS. LDB NLNCD GET MOVE COUNT. STB MCNTR SAVE IT. JSB MOVE MOVE DATA BLOCK. LDA FENVA GET OLD FENCE VALUE STA FENP1 SAVE IT INA INCREMENT AND SAVE NEW VALUE STA FENVA OTA FENCE LOAD FENCE REGISTER ADA OFSTM GET EXPECTED INTERRUPT ADDRESS STA EXPVR SAVE IT STC MPT TURN ON MPT JMP FENVA,I TRANSFER CONTROL TO TEST. RLOOP LDA BUFAD RESTORE DATA WHERE TEST MODULE LDB FENP1 IS RESIDING. STB BUFPT SAVE IT. LDB NLNCD GET MOVE COUNT. STB MCNTR SAVE IT. JSB MOVE MOVE DATA BLOCK. JMP TLOOP CONTINUE TEST. SKP * * *MOVE SUBROUTINE * MOVE NOP MLOOP LDB A,I GET A WORD. STB BUFPT,I STORE IT. INA MOVE ISZ BUFPT POINTERS. ISZ MCNTR DONE YET? JMP MLOOP NO! GO MOVE ANOTHER WORD. JMP MOVE,I YES! EXIT. * ***************************************************************** * * *TEST MODULE * STCOD DEF *+1 BELOW NOP NOP THIS WILL BE THE FENCE LOCATION STA FENVA,I STORE AT FENCE. NO INTERRUPT. MPTVL STA FENP1,I STORE BELOW FENCE. INTERRUPT. HLT 03 FORCE INT IN CASE OF BAD FENCE. JMP RLOP,I TRANSFER CONTROL BACK TO TEST. ***************************************************************** ENCOD EQU * LENCD EQU ENCOD-BELOW NLNCD ABS BELOW-ENCOD OFSET EQU MPTVL-BELOW-1 OFSTM DEF OFSET BUFAD DEF *+1 NOP NOP NOP NOP NOP NOP NOP SKP * * *TEST ABILITY OF AN I/O INSTRUCTION IN A TRAP * CELL NOT TO SHUT OFF MPT * MPT08 CLC 0,C TURN OFF I-O LDA BMPT A = MPT S/C JSB JSTRP TRAP CELL = JSB INT4 DEF INT4 LDA MP08D SET UP FENCE OTA FENCE STA FENVA LDA CFTBG A = CLF TBG STA TBG TRAP CELL = CLC TBG JSB ONTBG TURN ON TBG STC MTRAP TURN ON MPT NOP TBG INTERRUPT AFTER FIRST NOP NOP CLF0 CLC 0,C MPT VIOLATION SHOULD OCCUR HERE JSB PROER,I MPT VIOLATION DID NOT OCCUR * INT4 NOP MPT ROUTINE CLF 0 DISABLE INTERRUPTS LDA JSBIL GET JSB ILINT FOR TBG TRAP CELL STA TBG LOAD TRAP CELL SFC TBG DID TBG TICK AGAIN? JSB PROER,I YES - CLF IN TRAP CELL DID NOT EXECUTE LIA VIOLA,C NO - READ VIOLATION REGISTER CPA CLFAD COMPARE WITH EXPECTED VIOLATING ADDRESS RSS VIOLATIONG ADDRESS CORRECT JSB PROER,I WRONG INSTRUCTION CAUSED VIOLATION SFC TBG WAIT FOR TBG FLAG TO SET AGAIN JMP MPT09-1 IT SET. GO TO NEXT TEST ISZ A STILL CLEAR - INCREMENT COUNTER JMP *-3 CHECK FLAG AGAIN JSB CPUER,I TBG TURNED OFF BY CRS WITH MPT ON. * ONTBG NOP CLB CLF TBG CLEAR TBG FLAG STC TBG TURN ON TBG SFC TBG HAS TBG TICKED? JMP *+4 YES - GO ON ISZ B NO - GIVE IT TIME JMP *-3 JSB PROER,I TBG DID NOT TICK STF 0 JMP ONTBG,I RETURN TO PROGRAM * CLC 0,C AND WORLD SKP * *THIS VERIFIES THAT A MULTI-LEVEL INDIRECT * INSTRUCTION WILL BE INTERRUPTED DURING THE THIRD LEVEL MPT09 LDA B6 A = TBG S/C JSB JPTRP TRAP CELL = JMP ERR09 DEF ERR09 JSB ONTBG TURN ON TBG JMP *+1,I START MULTI-LEVEL DEF *+1 INDIRECT. NO INTERRUPT. CLC 0,C CLEAR INT SYSTEM. JSB JPTRP TRAP CELL = JMP E09.1 DEF E09.1 JSB ONTBG TURN ON TBG JMP *+1,I MULTI-LEVEL INDIRECT DEF *+1,I (TWO LEVELS-NO INTERRUPT). DEF *+1 CLC 0,C CLEAR INT. SYSTEM. JSB JSTRP TRAP CELL = JSB EXITM DEF EXITM JSB ONTBG TURN ON TBG JMP *+1,I THREE DEF *+1,I LEVEL DEF *+1,I INDIRECT. DEF *+1 INTERRUPT HERE. EXILP CLC 0,C NO INTERRUPT OCCURRED. JSB CPUER,I NO I/O INTERRUPT IN INDIRECT CHAIN ERR09 JSB CPUER,I INTERRUPT AFTER 1ST LEVEL INDIRECT E09.1 JSB CPUER,I INTERRUPT AFTER 2ND LEVEL INDIRECT EXILA DEF EXILP EXILB DEF EXILQ EXITM NOP LDA EXITM CHECK RETURN ADDRESS CPA EXILA ?? RSS OK JSB CPUER,I NO CLC 0,C CLEAR THE I/O SYSTEM LDA B6 A = TBG S/C JSB JSTRP TRAP CELL = JSB EXITN DEF EXITN JSB ONTBG TURN ON TBG EXILQ JMP *+1,I FOUR DEF *+1,I LEVELS DEF *+1,I OF INDIRECT DEF *+1,I DEF *+1 CLC 0,C TURN OFF INTERRUPTS JSB CPUER,I INTERRUPT ALLOWED AFTER INDIRECT CHAIN EXITN NOP LDA EXITN CHECK RETURN ADDRESS CPA EXILB IS IT RIGHT?? RSS JSB CPUER,I INTERRUPT ALLOWED AFTER INDIRECT CHAIN LDA JSBIL RESTORE JSB ILINT TO TRAP CELL STA MTRAP STA TRP06 CLC 0,C TURN EVERY THING OFF * *PROCESSOR INTERRUPT PRIORITY TEST. CHECKS THAT PARITY * * INTERRUPT IS SERVICED BEFORE A UIT OR A MEMORY PROTECT * * INTERRUPT. IF UI OR MP INTERRUTS OCCUR AHEAD OF * * PARITY ERROR INTERRUPTS, AN ILLEGAL INTERRUPT WILL * * BE INDICATED. * PRIPR LDA B7 LOAD 7 INTO THE STA CNTR SUBSECTION COUNTER LDA B2000 LOAD LOCATION 2000 OTA FENCE AND LOAD INTO THE FENCE CLC PES TURN OFF PARITY INTERRUPTS LDA BDN1,I BDN == INSTR. TO STORE BELOW FENCE LDB UI UI = UNIMPLEMENTED INSTRUCTION STF PES REVERSE PARITY SENSE SFC PES DOES SFS AND SFS PES SFC WORK? JSB PROER,I NO - FAILURE STA BDI STORE VIOLATING MP INSTR. W/ BAD PARITY STB BUI.1 STORE UI W/ BAD PARITY CLF PES RESET PARITY SENSE SFS PES DOES SFS AND SFC PES SFC WORK? JSB PROER,I NO - FAILURE LDA B5 SET UP NEW PARITY INTERRUPT RETURN JSB JPTRP TRAP CELL 5= JMP PRI.1 DEF PRI.1 STC PES TURN ON PARITY INTERRUPTS STC MPT TURN ON MEMORY PROTECT BDI NOP INSTR. W/ BAD PARITY.STORE BELOW FENCE STA BDI NO INTERRUPT OCCURRED JSB PROER,I GO SHOW ERROR PRI.1 STA BDI INTERRUPT WAS HANDLED CORRECTLY LDA B5 SET UP NEW PARITY INTERRUPT TRAP CELL JSB JPTRP TRAP CELL 5 = JMP PRI.2 DEF PRI.2 LDA B10 RESET COUNTER FOR STA CNTR UIT STC PES TURN ON PARITY SYSTEM BUI.1 NOP INSTR. W/ BAD PARITY -- UI STA BUI.1 RESTORE GOOD PARITY JSB PROER,I DIDN'T INTERRUPT PRI.2 STA BUI.1 INT. GOOD -- RESTORE GOOD PARITY JSB RSTRP RESTORE TRAP CELL 5 STC PES TURN ON PARITY SYSTEM * * *PROCESSOR TESTS COMPLETE. GO TEST I/O SYSTEM. HED I/O CHIP TESTS - REGISTERS AND FLAGS * * *BASIC CPU FUNCTIONS WORK. CHECK THE I/O CHIPS. * * *SET UP A TABLE OF ALL SYSTEM SELECT CODES * CHIPS LDA B13 GET STATUS = SETTING S/C TABLE OTA LEDS OUTPUT TO LEDS CLC 0,C CLEAR THE I/O SYSTEM CLA,INA SET DIAGNOSE MODE 1 OTA GR GIVE TO CHIPS LDA SCTAD GET S/C TABLE ADDRESS = SCTBL STA POINT SET POINTER TO THE BEGINNING-1 GETSC CLA IN CASE OF NO RESPONSE ISZ POINT READY FOR NEXT ENTRY LIA GR GET A SELECT CODE SZA,RSS DID ONE COME BACK? JMP NOSC NO AND SCM YES - USE THE SELECT CODE AND BIT 15 STA POINT,I STORE IT IN THE SELECT CODE TABLE ELA,CLE,ERA STA TMP0 SAVE SC ONLY AND B70 SZA,RSS IS IT A VALID SELECT CODE? JSB IOER,I NO LDA SCTAD YES INA SET A TO FIRST ENTRY DUPSC LDB A CHECK FOR DUPLICATE S/C'S CPB POINT END OF TABLE? JMP GETSC YES - MOVE TO NEXT CHIP LDB A,I NO - GET S/C FROM TABLE CPB TMP0 IS IT THE SAME AS THE NEW S/C? JSB IOER,I YES INA JMP DUPSC NO - CHECK NEXT ENTRY NOSC LDA SCTBL+1 HAVE ANY S/C'S BEEN ENTERED? SZA,RSS JSB IOER,I NO, SO NO I/O CHIPS RESPONDED. ERROR LDA SCTAD YES, SO THE S/C TABLE IS COMPLETE STA POINT RESET POINTER TO BEGINNING-1 CLA DISABLE DIAGNOSE MODE 1 OTA GR * * *NOTE: IF OTA OR LIA GR FAILED, THE CODE WILL ERROR OUT EITHER * AT THE POINT INDICATING NO IO CHIPS, OR AT THE POINT * INDICATING DUPLICATE IO CHIPS SKP * *CHECK IF A BAD PRIORITY CHAIN PREVENTED * ANY I/O CHIPS FROM RESPONDING * TST06 LDA B7 START WITH 10 ISZ POINT STA TEMP3 TEMP3 IS THE COUNTER MIS.1 ISZ TEMP3 INCREMENT THE COUNTER LDA POINT GET THE TABLE ADDRESS MIS.2 LDB A,I B = CURRENT S/C TABLE ENTRY SZB,RSS END OF THE TABLE? JMP NOTIN S/C UNDER TEST NOT IN TABLE ELB,CLE,ERB CPB TEMP3 IS S/C UNDER TEST = TABLE ENTRY? JMP MIS.1 YES - TEST NEXT SELECT CODE INA NO - CHECK NEXT TABLE ENTRY JMP MIS.2 NOTIN LDB TEMP3 GET S/C UNDER TEST CPB B100 HAVE ALL S/C'S BEEN CHECKED? JMP GRTST YES OTB GR,C NO - TRY TALKING TO THIS S/C CLA LIA GR SZA DID ANYTHING COME BACK? JSB IOER,I YES - IT SHOULDN'T HAVE JMP MIS.1 NO - TEST NEXT SELECT CODE SKP * * *CHECK EACH CHIP'S REGISTERS AND FLAGS * * * *CHECK ALL THE GLOBAL REGISTERS * GRTST JSB CLC0,I CLEAR & DISABLE DIAGNOSE MODE 1 LDA B7 SET UP A SELECT CODE COUNTER OTA GR ESTABLISH DIAGNOSE MODE SEVEN STA TEMP3 TEMP3 IS THE COUNTER GRT.1 LDA B2 ESTABLISH DIAGNOSE MODE 2 OTA GR LDB SCTAD SET POINTER TO BEGINNING-1 STB POINT CLA STA TEMP4 CLEAR TEMP4 ISZ TEMP3 INCREMENT SELECT CODE COUNTER LDA TEMP3 HAVE ALL S/C'S BEEN CHECKED? CPA B100 JMP REGFL YES - DO NEXT TEST OTA GR NO - OUTPUT S/C TO GR GRT.2 ISZ POINT MOVE TO NEXT TABLE ENTRY LDB POINT,I GET NEXT TABLE SELECT CODE SZB,RSS IS THIS THE END OF THE TABLE? JMP GRT.1 YES - CHECK THE NEXT SELECT CODE ELB,CLE,ERB LDA TEMP3 GET S/C UNDER TEST FROM COUNTER CPA B IS S/C UNDER TEST = TO TABLE ENTRY? ISZ TEMP4 YES - REMEMBER THAT IT'S EQUAL LIA GR GET STATUS FROM CURRENT I/O CHIP STA TEMP5 SAVE STATUS AND B77 MASK OUT SELECT CODE CPA TEMP3 IS S/C IN STATUS = S/C SENT TO GR? RSS YES JSB IOER,I NO LDB TEMP4 DID S/C UNDER TEST = TABLE ENTRY? SZB JMP EQUAL YES NOTEQ LDA TEMP5 NO - GET STATUS AGAIN AND PAT16 MASK IRRELEVANT BITS CPA PAT17 IS STATUS CORRECT? RSS JSB IOER,I NO JMP GRT.2 YES - TEST NEXT I/O CHIP EQUAL LDA TEMP5 GET STATUS AGAIN AND PAT16 PRIO,DF3,CNTRL,FLAG,GR=SC,GREN CPA PAT20 IS STATUS CORRECT? RSS PRIORITY AND GR=S/C ONLY JSB IOER,I NO CLA CLEAR TEMP4 STA TEMP4 JMP GRT.2 YES - TEST NEXT I/O CHIP SKP * * *CHECK CHIP DATA PATHS AND THAT MERGE WORKS * REGFL LDA SCTAD SET POINTER TO BEGINNING-1 STA POINT SETSC JSB CLC0,I ISZ POINT GET THE NEXT CHIP SELECT CODE LDA POINT,I SZA,RSS IS THIS THE END OF THE TABLE? JMP NTSAD,I YES - GO TEST INTERRUPTS OTA GR,C NO - ENABLE THE GLOBAL REGISTER SFC GR IS GR ENABLED? JSB IOER,I NO CLA YES - NOW CHECK DATA BUS BUSCK OTA CWRD1 OUTPUT DATA TO CHIP LIB CWRD1 INPUT DATA FROM CHIP CPA B IS DATA CORRECT? RSS JSB IOER,I NO ISZ A YES - INCREMENT THE DATA, REPEAT JMP BUSCK LDB PAT02 BUS OK; VERIFY THAT MERGE WORKS OTB CWRD1 SET UP CWRD1 LDB PAT03 GET EXPECTED RESULT LDA PAT04 SET UP A MIA CWRD1 EXECUTE THE MERGE CPA B WAS THE MERGE CORRECT? RSS JSB IOER,I NO SKP * * *CHECK ALL REGISTERS * LIA N1 GET CONTENTS OF 25 STA TEMP9 AND STORE TEMPORARILY LDB PAT02 GET THE FIRST TEST PATTERN REGCK OTB INMSK WRITE INTERRUPT MASK REGISTER OTB CONAD WRITE CONFIGURATION ADDRESS REG LIA CONAD CHECK IF BIT 15 IS ALWAYS A ONE SSA,RSS IS IT A ONE? JSB IOER,I NO OTB CWRD1 WRITE DMA CONTROL WORD 1 REG OTB WRDCT WRITE DMA WORD COUNT REGISTER OTB DMAAD WRITE DMA ADDRESS REGISTER OTB N1 WRITE N1 REGISTER OTB N2 WRITE N2 REGISTER OTB M2 WRITE M2 REGISTER STB TEMP0 STORE PATTERN TEMPORARILY LDA POINT,I GET GLOBAL REGISTER LDB B2 INSTRUCTION TO READ JSB IRGC1 GO CHECK IT JSB IOER,I LI* OR MI* 2 FAILED LDB TEMP0 GET PAT02 AGAIN LIA INMSK MERGE INTO A FROM INT MASK REG AND PAT14 MASK OFF BIT 0 MIA CWRD1 OR WITH CONT WORD 1 REG MIA WRDCT OR WITH WORD COUNT REG STA TEMP0 SAVE CONTENTS OF A LIA DMAAD GET DMA ADDR REG DATA MIA CONAD OR WITH CONF ADDR REG MIA DMAAD OR WITH DMA ADDR. AND PAT15 MASK OFF BIT 15 IOR TEMP0 OR WITH SAVED CONTENTS OF A MIA N1 OR WITH N1 REG MIA N2 OR WITH N2 REG MIA M2 OR WITH M2 REG CPA B WAS THE DATA CORRECT? RSS JSB IOER,I NO CMB YES - INVERT PATTERN CPB PAT02 HAVE BOTH PATTERNS BEEN CHECKED? RSS YES JMP REGCK NO - DO NEXT PATTERN LIA DMAAD CHECK THAT DMA ADDR BIT 15 WORKS SSA,RSS CWRD1 BIT 7 = 0; IS DMAAD 15 = 1? JSB IOER,I NO OTB CWRD1 CWRD1 BIT 7 = 1 LIA DMAAD GET DMA ADDR REG CONTENTS SSA IS BIT 15 = 0? JSB IOER,I NO JSB CLC0,I CLEAR I/O CLF GR AND RE-ENABLE GLOBAL REG. SKP * * *CHECK DEVICE FLAG WITH GR ENABLED * *ALSO CHECK PARITY IO INTERRUPTS. * FLAGS SFC DF3 FLAGS 20, 21, 22 CLEAR? SFC WORK? JSB IOER,I NO SFC DF0 DOES SFC 20 WORK? (USED LATER) JSB IOER,I NO STF GSC SET THE DEVICE FLAG (30) W/ GR ENABLED SFC GSC CHECK IF FLAG SET, SFS AND SFC SFS GSC IS FLAG SET? JSB IOER,I NO. FLAG CLEAR OR SFS-SFC BOMBED CLF GSC YES - CLEAR THE FLAG SFS GSC IS FLAG CLEAR? AND DO SFS-SFC SFC GSC DETECT IT? JSB IOER,I NO. FLAG NOT SET OR SFS-SFC BOMBED STF GR YES - DISABLE THE GR SKP * * *CHECK DEVICE FLAG WITH GR DISABLED * FLAG1 LDB POINT,I GET CURRENT SELECT CODE LDA B7 NUMBER OF INSTRUCTIONS TO CHANGE JSB MDSC,I GO TO SUBROUTINE STF SC SET FLAG SFC SC IS FLAG SET? AND DO SFS-SFC SFS SC DETECT IT? JSB IOER,I NO. FLAG NOT SET OR SFS-SFC FAILED CLF SC YES - CLEAR THE FLAG SFS SC IS FLAG CLEAR? AND DO SFS-SFC SFC SC DETECT IT? JSB IOER,I NO. FLAG NOT CLEAR OR SFS-SFC FAILED CLF GR YES - ENABLE THE GR STF GSC VERIFY I/O CHIP PARAMETERS CLC GSC INSURE CONTROL IS OFF LDA B2 ESTABLISH DIAGNOSE MODE 2 OTA GR LDA POINT,I A = S/C UNDER TEST IOR LIASC A = LIA CHIP SELECT CODE STA M2SET M2SET = LIA S/C M2SET NOP RESERVED FOR LIA FROM CURRENT S/C AND PAT23 RETAIN CONTROL,FLAG,GR=S/C?,GREN? XOR PAT27 MASK BITS SZA PARAMETERS CORRECT? JSB IOER,I NO OTA GR DISABLE DIAGNOSE MODE 2 CLC GSC,C CLEAR FLAG,CONTROL STF GR DISABLE GLOBAL REGISTER LDA B2 ESTABLISH DIAGNOSE MODE 2 OTA GR LDA M2SET GET LIA S/C INSTRUCTION STA M2CLR M2CLR = LIA S/C M2CLR NOP RESERVED FOR LIA FROM CURRENT S/C AND PAT32 RETAIN CONTROL,FLAG,GR=S/C?,GREN? XOR PAT30 MASK BITS; GR=S/C SHOULD BE A 1 SZA PARAMETERS CORRECT? JSB IOER,I NO OTA GR,C A=0, DISABLE DIAGNOSE MODE 2 SKP * * *ROTATE A PATTERN THROUGH EACH REGISTER * CCE INITIALIZE E LDA PAT06 GET THE PATTERN ROTAT RAL ROTATE DATA LEFT OTREG STA TEMP1 SAVE THE PATTERN IN A OTA INMSK WRITE INTERRUPT MASK REGISTER AND PAT14 MASK OFF BIT 0 STA TEMP2 SAVE THE PATTERN CLA CLEAR A MIA INMSK READ BACK FROM INTERRUPT MASK AND PAT14 MASK OFF BIT 0 CPA TEMP2 DATA CORRECT? RSS YES JSB IOER,I NO - MERGE FAILED OR DATA INCORRECT LDA TEMP1 GET CURRENT PATTERN IOR PAT10 ADD BIT 15 TO PATTERN OTA CONAD WRITE CONFIGURATION ADDRESS REG LIB CONAD READ BACK CPA B DATA CORRECT? RSS YES JSB IOER,I NO LDA TEMP1 GET CURRENT PATTERN OTA CWRD1 WRITE DMA CONTROL WORD 1 REG LIB CWRD1 READ BACK CPA B DATA CORRECT? RSS YES JSB IOER,I NO OTA WRDCT WRITE DMA WORD COUNT REGISTER LIB WRDCT READ BACK CPA B DATA CORRECT? RSS YES JSB IOER,I NO OTA DMAAD WRITE DMA ADDRESS REGISTER AND PAT15 MASK OFF BIT 15 STA TEMP2 SAVE THE PATTERN LIA DMAAD READ BACK DMA ADDRESS REGISTER AND PAT15 MASK OFF BIT 15 CPA TEMP2 DATA CORRECT? RSS YES JSB IOER,I NO * * (CONTINUED) * SKP LDA TEMP1 GET CURRENT PATTERN OTA N1 WRITE N1 REGISTER LIB N1 READ BACK CPA B DATA CORRECT? RSS YES JSB IOER,I NO OTA N2 WRITE N2 REGISTER LIB N2 READ BACK CPA B DATA CORRECT? RSS YES JSB IOER,I NO OTA M2 WRITE M2 REGISTER LIB M2 READ BACK CPA B DATA CORRECT? RSS YES JSB IOER,I NO CMA COMPLEMENT DATA SEZ,CME HAS THE COMPLEMENT BEEN CHECKED? JMP OTREG NO - CHECK IT CPA PAT06 YES - WAS THAT LAST PATTERN? RSS YES JMP ROTAT NO - DO NEXT PATTERN SKP * * *CHECK FOR CROSSTALK BETWEEN REGISTERS LDA B2 SET A = 2 CROSS STA B STORE CURRENT PATTERN IN B OTA INMSK WRITE 000002 TO INT MASK REG INA OTA CONAD WRITE 000003 TO CONF ADDR REG INA OTA CWRD1 WRITE 000004 TO CONT WORD 1 REG INA OTA WRDCT WRITE 000005 TO WORD COUNT REG INA OTA DMAAD WRITE 000006 TO DMA ADDR REG INA OTA N1 WRITE 000007 TO N1 REG INA OTA N2 WRITE 000010 TO N2 REG INA OTA M2 WRITE 000011 TO M2 REG STB TEMP3 SAVE B LDA B AND PAT14 MASK OFF BIT 0 LDB A PUT MODIFIED PATTERN IN B LIA INMSK CHECK IF CROSSTALK OCCURRED. GET INMSK AND PAT14 MASK OFF BIT 0 CPA B DATA CORRECT? RSS YES JSB IOER,I NO LDB TEMP3 RESTORE B INB LIA CONAD GET CONF ADDR DATA AND PAT15 MASK OFF BIT 15 CPA B DATA CORRECT? RSS YES JSB IOER,I NO INB LIA CWRD1 GET CONT WORD 1 DATA CPA B DATA CORRECT? RSS YES JSB IOER,I NO INB LIA WRDCT GET WORD COUNT DATA CPA B DATA CORRECT? RSS YES JSB IOER,I NO INB LIA DMAAD GET DMA ADDRESS DATA AND PAT15 MASK OFF BIT 15 CPA B DATA CORRECT? RSS YES JSB IOER,I NO * * (CONTINUED) * SKP INB LIA N1 GET N1 DATA CPA B DATA CORRECT? RSS YES JSB IOER,I NO INB LIA N2 GET N2 DATA CPA B DATA CORRECT? RSS YES JSB IOER,I NO INB LIA M2 GET M2 DATA CPA B DATA CORRECT? RSS YES JSB IOER,I NO RAL ROTATE PATTERN LEFT ONE SSA,RSS HAVE ALL PATTERNS BEEN CHECKED? JMP CROSS NO - CHECK THIS PATTERN CLC PES TURN OFF PARITY INT. STF PES REVERSE SENSE LDA BIOIS GET GOOD INSTR., REVERSE STA BIOIN SENSE AND STORE IN-LINE CLF PES RESET SENSE STC PES TURN ON SYSTEM LDA B5 LOAD NEW PAROITY INTERRUPT ADDRESS JSB JPTRP INTO TRAP CELL 5 DEF PIO1 CCA SET A TO ALL ONE'S BIOIN NOP TRY TO EXECUTE BAD INSTR. STA BIOIN CLEAR INSTRUCTION LOCATION JSB IOER,I NO INTERRUPT OCCURRED PIO1 STC PES TURN SYSTEM BACK ON AFTER INTERRUPT STA BIOIN RESTORE GOOD PARITY IN L0CATION SFC GSC DID INSTRUCTION EXECUTE? JSB IOER,I YES SO ERROR JSB RSTRP RESTORE TRAP CELL LDA TEMP9 GET ORIGINAL CONTENTS OF 25 OTA N1 AND SEND BACK TO 25 * * *THIS I/O CHIP'S REGISTERS AND NON-DMA FLAGS ARE GOOD * JMP SSC,I CHECK THE NEXT I/O CHIP SKP * *SELECT CODE MODIFICATION ROUTINE FOR I/O INSTRUCTIONS * * ORG 16000B MODSC NOP RETURN ADDRESS CMA,INA TWO'S COMPLEMENT NUMBER OF INSTR. STA TEMP0 STORE IN REG. LDA MODSC GET ADDRES OF FIRST INSTRUCTION STA TEMP1 STORE IN REG. MOD.1 LDA TEMP1,I GET FIRST INSTRUCION SSA,RSS IS BIT 15 1?(POSSIBLE I/O INSTRUCTION) JMP MODNX NO. GET NEXT INSTRUCTION AND PAT33 MASK WITH 172000 OCTAL CPA PAT34 COMPARE WITH 102000 OCTAL(I/0 INSTR. FORMAT) RSS JMP MODNX NOT EQUAL. TRY ANOTHER INST. LDA TEMP1,I GET INSTR. AGAIN AND B70 AND IT WITH 70 OCTAL SZA,RSS SKIP IF NOT ZERO JMP MODNX GO DO NEXT INSTRUCTION LDA TEMP1,I GET INSTRUCTION AGAIN AND PAT00 MASK WITH 177700 OCTAL IOR B PUT IN NEW SELECT CODE STA TEMP1,I RESTORE IT MODNX ISZ TEMP1 INCREMENT ADDRESS POINTER ISZ TEMP0 INCREMENT INSTR. COUNTER JMP MOD.1 DO IT AGAIN JMP MODSC,I END OF SUBROUTINE WHEN COUNT=0 HED I/O CHIP TESTS - NON-DMA INTERRUPTS * * *NOW THE INTERRUPT SYSTEM WILL BE CHECKED * TST07 RSS OR JSB CNTL JMP TST08 NOP LDA SCTAD SET TABLE POINTER TO BEGINNING-1 STA POINT INT.1 CLA CLEAR INTERRUPT MASK REGISTER OTA INMSK STA TEMP2 CLEAR TEMP2 INT.2 ISZ POINT INCREMENT S/C TABLE POINTER LDA POINT,I GET NEXT CHIP SELECT CODE SZA,RSS IS THIS THE END OF THE TABLE? JMP TST08 YES - GO TEST DMA OTA GR,C NO - LOAD GLOBAL REGISTER LDB B2 ESTABLISH DIAGNOSE MODE 2 OTB GR IOR LIASC A = LIA S/C STA INT.3 INT.3 = LIA S/C INT.3 NOP RESERVED FOR LIA FROM CURRENT S/C AND PAT21 SAVE PRIORITY BIT XOR PAT21 DOES CHIP HAVE PRIORITY? SZA JSB IOER,I NO OTA GR,C YES - DISABLE DIAGNOSE MODE 2 * * CHECK THAT AN I/O INSTR. IN TRAP CELL GETS EXECUTED * CCA STORE A -1 OTA M2 IN 24 LDB IORTN STORE RETURN ADDRESS IN B LDA LIA24 GET THE INSTRUCTION JMP A GO DO IT IORT1 CMA,SZA DID INSTRUCTION EXECUTE? JSB IOER,I NO - GO INDICATE SKP * * *CHECK INTERRUPT REQUEST HANDLING * LDA POINT,I GET THE CURRENT CHIP S/C ELA,CLE,ERA JSB JPTRP SET UP TRAP CELL = JMP INT.4 DEF INT.4 STF DF2 FORCE AN INTERRUPT FROM CHIP STF 0 ENABLE INTERRUPTS ISZ TEMP2 SHOULD INTERRUPT AFTER 1 ISZ TEMP2 ISZ TEMP2 EXECUTED? INTERRUPTED AT WRONG TIME JSB IOER,I NO INTERRUPT INT.4 CLF 0 TURN OFF THE INTERRUPT SYSTEM CLF DF2 TURN OFF PARITY INTERRUPT JSB RSTRP INTERRUPT GOOD. RESTORE TRAP CELL LDB TEMP2 CHECK WHERE INTERRUPT OCCURRED CPB B1 WAS IT AFTER FIRST ISZ TEMP2? RSS YES JSB IOER,I NO STF DF2 WILL CLF 0 PREVENT INTERRUPTS? NOP GIVE IT TIME;NO INT. SHOULD OCCUR NOP IF INT. OCCURS JSB ILINT STF 0 CAN INTERRUPTS BE HELD OFF STF DF0 BY I/O INSTRUCTIONS? ALL INSTR. CLF DF0 SHOULD EXECUTE WITHOUT AN INT. SFS DF0 OCCURRING. IF ONE DOES, JSB ILINT SFC DF0 LIA 7,C MIA 7,C OTA 7 JMP *+1,I HELD OFF BY JMP,I? DEF *+1 JSB *+1,I HELD OFF BY JSB,I? DEF *+1 NOP CLF DF2 HELD OFF BY CLEARING THE FLAG? NOP GIVE IT TIME. NO INT. SHOULD OCCUR NOP SINCE FLAG HAS BEEN CLEARED. SKP * * *CHECK TO SEE IF MORE THAN ONE INTERRUPT OCCURS * FROM EACH CHIP * LDA POINT,I A = CHIP S/C UNDER TEST ELA,CLE,ERA JSB JSTRP SET TRAP CELL = JSB INT.5 DEF INT.5 STF DF2 FORCE AN INTERRUPT NOP GIVE IT TIME JSB IOER,I NO INTERRUPT OCCURRED INT.5 NOP LDA INT.5 GET RETURN ADDRESS CPA .5RTN DID A SECOND INTERRUPT OCCUR? RSS NO JSB IOER,I YES, MULTIPLE INTERRUPTS OCCURRED CLF DF2 CLEAR CHIP FLAG LDA POINT,I A = CHIP S/C UNDER TEST ELA,CLE,ERA * * *CHECK IF CLC 0 PREVENTS INTERRUPTS * ISZ TEMP2 TEMP2=2 ISZ TEMP2 TEMP2=3 STF DF2 NOW FORCE AN INTERRUPT CLC 0 CAN CLC 0 PREVENT INTERRUPTS? NOP GIVE IT TIME JSB CLC0,I TURN OFF INTERRUPTS AND CHECK CARDS CLF GR ENABLE GLOBAL REGISTER CLF DF2 CLEAR FLAG ON CHIP UNDER TEST SKP * * *NOW CHECK THE INTERRUPT MASK REGISTER BY * GENERATING THE PATTERN TO MASK THE CURRENT CHIP * AND THEN ATTEMPTING INTERRUPTS. THEN MASK ALL BUT * THE CURRENT CHIP AND INTERRUPT. EACH TIME THE * INTERRUPT MASK IS ALTERED INSURE THAT THE NEXT LOWER * PRIORITY I/O CHIP IS CORRECTLY GIVEN PRIORITY BY * THE CHIP UNDER TEST OR THAT PRIORITY IS REMOVED. * MSKCK LDB B1ADR GET ADDRESS OF CONSTANT TABLE STB TEMP3 SAVE THE ADDRESS LDB PAT22 BEGIN FORMING PATTERN. B = 000004 LDA POINT,I A = CHIP S/C UNDER TEST AND B70 RETAIN HIGH ORDER BITS RAR,RAR SHIFT HIGH BITS TO LOW POSITION RAR WCHSC CPA TEMP3,I DO THE HIGH ORDER BITS MATCH? JMP MATCH YES RBL,RBL NO - ROTATE MASK PATTERN LEFT TWICE ISZ TEMP3 MOVE TO NEXT CONSTANT JMP WCHSC CHECK THE NEXT VALUE MATCH LDA POINT,I A = CHIP S/C UNDER TEST ELA,CLE,ERA RAR,RAR LOOK AT S/C BIT 2 SLA IS IT A 1? RBL YES, ROTATE PATTERN LEFT ONCE MORE SFC DF0 WAS THE LAST ROUTINE USED BY DMA? JMP BACK YES - OTB INMSK AND RETURN TO DMA JSB CKPRI NO. CHECK PRIORITY ON THE NEXT CHIP SEZ,RSS DID IT HAVE PRIORITY? JSB IOER,I NO, BUT IT SHOULD HAVE STF DF2 FORCE A INTERRUPT FROM CHIP JSB CKPRI WANTS TO INTERRUPT. CHECK NEXT PRIORITY SEZ DID IT HAVE PRIORITY? JSB IOER,I YES, BUT IT SHOULDN'T HAVE OTB INMSK MASK CURRENT CHIP STF TBG SET FLAG INDICATING INMSK TEST JSB CKPRI CHECK PRIORITY OF NEXT CHIP SEZ,RSS DOES NEXT CHIP HAVE PRIORITY? JSB IOER,I NO, BUT IT SHOULD HAVE CMB COMPLEMENT MASK OTB INMSK MASK ALL BUT CURRENT CHIP JSB CKPRI CHECK PRIORITY OF NEXT CHIP SEZ DOES NEXT CHIP HAVE PRIORITY? JSB IOER,I YES, BUT IT SHOULDN'T HAVE CMB SET B TO ORIGINAL INMSK VALUE CLC GSC,C CLEAR CONTROL AND FLAG ON CURRENT CHIP * * (CONTINUED) * SKP MSK.1 OTB INMSK PATTERN IS CORRECT SET INTERRUPT MASK LIA INMSK GET INMSK FROM CHIP UNDER TEST SLA,RSS IS THIS CHIP MASKED? JSB IOER,I INMSK THINKS S/C IS NOT MASKED LDA POINT,I GET CHIP S/C UNDER TEST ELA,CLE,ERA JSB JPTRP TRAP CELL = JMP INT.7 DEF INT.7 STF DF2 TRY TO FORCE AN INTERRUPT STF 0 ENABLE INTERRUPTS NOP GIVE IT TIME RSS NO INTERRUPT HAS OCCURRED INT.7 JSB IOER,I THE INTERRUPT OCCURRED ILLEGALLY CLF 0 DISABLE INTERRUPTS LIA INMSK GET INTERRUPT MASK CMA MASK ALL S/C'S EXCEPT CURRENT CHIP OTA INMSK LDA POINT,I A = CHIP S/C UNDER TEST ELA,CLE,ERA JSB JPTRP TRAP CELL = JMP INT.8 DEF INT.8 STF 0 ALLOW THE INTERRUPT NOP GIVE IT TIME JSB IOER,I NO INTERRUPT INT.8 CLF DF2 INTERRUPT GOOD - CLEAR CHIP FLAG JSB RSTRP RESTORE JSB ILINT TO TRAP CELL JSB CLC0,I CLEAR ALL I/O * * *THIS CHIP INTERRUPTS CORRECTLY * JMP INT.1 TEST NEXT CHIP'S INTERRUPTS SKP * * *SUBROUTINE TO CHECK PRIORITY OF NEXT LOWER * PRIORITY I/O CHIP * CKPRI NOP RESERVED FOR RETURN ADDRESS DST SAVA SAVE A AND B LDA POINT,I GET CURRENT I/O CHIP S/C ELA,CLE,ERA STA TEMP1 SAVE IT IN TEMP1 ISZ POINT MOVE POINTER TO NEXT I/O CHIP S/C LDA POINT,I GET NEXT CHIP S/C ELA,CLE,ERA STA TEMP0 SAVE IT IN TEMP0 CCA DECREMENT POINTER ADA POINT STA POINT LDA TEMP0 A = NEXT CHIP S/C SZA,RSS IS THERE A NEXT CHIP? JMP MSK.1 NO - CONTINUE TESTING THE CURRENT CHIP OTA GR YES - GIVE S/C TO GR SFC TBG HAS THE INMSK TEST BEGUN? JSB NXMSK YES - ARE CURRENT AND NEXT BOTH MASKED? LDB B2 NO - ESTABLISH DIAGNOSE MODE 2 ON NEXT OTB GR LDA TEMP0 GET NEXT CHIP S/C IOR LIASC GET LIA SC FOR MODIFICATION STA GETPR PUT INSTRUCTION IN LINE GETPR LIA SC RESERVED FOR LIA FROM NEXT S/C AND PAT17 DOES NEXT CHIP HAVE PRIORITY? CCE SZA CLE CME IF NO, CLEAR E. IF YES, SET E CLA DISABLE DIAGNOSE MODE 2 OTA GR LDA TEMP1 RESTORE GR TO CURRENT S/C OTA GR DLD SAVA RESTORE A AND B JMP CKPRI,I RETURN TO PROGRAM BACK OTB INMSK MASK CURRENT CHIP JMP FLG11 RETURN TO DMA TEST NXMSK NOP CLC TBG,C CLEAR TBG FLAG LIA INMSK GET INMSK FROM NEXT CHIP SLA IS CHIP MASKED? JMP SAMSK YES - SKIP INMSK TEST JMP NXMSK,I NO - RETURN TO PRIORITY CHECK SAMSK LDA TEMP1 RESTORE GR TO CURRENT S/C OTA GR DLD SAVA RESTORE A AND B CLC GSC,C CLEAR CONTROL AND FLAG ON CURRENT CHIP JMP MSK.1 CONTINUE TESTING CURRENT CHIP * * *THE I/O CHIPS ALL INTERRUPT CORRECTLY. HED I/O CHIP TESTS - DMA FUNCTIONS * *THE DMA TEST * * *TEST FLAGS ON S/C'S 20, 21, 22, AND 23 * TST08 EQU * DMATS LDA SCTAD SET TABLE POINTER TO BEGINNING-1 STA POINT DMAT1 ISZ POINT INCREMENT THE S/C TABLE POINTER LDA POINT,I GET THE NEXT CHIP S/C ELA,CLE,ERA SZA,RSS IS THIS THE END OF THE TABLE? JMP ALLAD,I YES - GO TEST MULTI INTERRUPTS OTA GR,C NO - LOAD THE GLOBAL REGISTER LDA B7 ESTABLISH DIAGNOSE MODE 7 OTA GR STF 0 ENABLE INTERRUPTS STF DF0 SET FLAG 20 SFC DF0 IS IT SET? AND DO SFS-SFC WORK? SFS DF0 JSB IOER,I NO. FLAG NOT SET OR SFS-SFC FAILED CLF DF0 CLEAR FLAG 20 SFS DF0 IS IT CLEAR? AND DO SFS-SFC WORK? SFC DF0 JSB IOER,I NO. FLAG NOT CLEAR OR SFS-SFC FAILED STF DF0 SET THE INMSK FOR THIS S/C JMP MSKCK FLG11 CLF DF0 CLEAR FLAG 20 STF DF1 SET FLAG 21 SFC DF1 IS IT SET? AND DO SFS-SFC WORK? SFS DF1 JSB IOER,I NO. FLAG NOT SET OR SFS-SFC FAILED CLF DF1 CLEAR FLAG 21 SFS DF1 IS IT CLEAR? AND DO SFS-SFC WORK? SFC DF1 JSB IOER,I NO. FLAG NOT CLEAR OR SFS-SFC FAILED STF DF2 SET FLAG 22 SFC DF2 IS IT SET? AND DO SFS-SFC WORK? SFS DF2 JSB IOER,I NO. FLAG NOT SET OR SFS-SFC FAILED CLF DF2 CLEAR FLAG 22 SFS DF2 IS IT CLEAR? AND DO SFS-SFC WORK? SFC DF2 JSB IOER,I NO. FLAG NOT CLEAR OR SFS-SFC FAILED SFC DF3 ARE FLAGS 20-22 CLEAR? DOES SFC WORK? JSB IOER,I NO * * (CONTINUED) SKP STF DF0 SET FLAGS 20-22 STF DF1 STF DF2 STF DF3 SFS DF3 IS ANYONE SET? DOES SFS WORK? JSB IOER,I NO SFS DF0 IS 20? JSB IOER,I NO SFS DF1 IS 21? JSB IOER,I NO SFS DF2 IS 22? JSB IOER,I NO CLF DF0 CLEAR FLAG 20 SFS DF1 DID 21B GET CLEARED? SFS DF3 IS ANYONE SET? JSB IOER,I NO STF DF0 SET FLAG 20 CLF DF2 CLEAR FLAG 22 SFC DF3 IS EVERYONE CLEAR? SFS DF3 IS ANYONE SET? JSB IOER,I NO. STF DF3 SET 23 CLF DF3 CLEAR FLAGS 20-22 AND 23 SFC DF3 IS EVERYONE CLEAR? JSB IOER,I NO SKP * * *FLAGS WORK. TEST CONTROLS AND INTERRUPTS * CCA STORE A -1 IN STA DMP01+2 WORD COUNT CLA CLEAR THE INTERRUPT MASK REGISTER OTA INMSK OTA CWRD1 CLEAR CONTROL WORD 1 LDA POINT,I GET THE CHIP S/C UNDER TEST ELA,CLE,ERA JSB JPTRP TRAP CELL = JMP DMA.1 DEF DMA.1 STC DF1 FORCE AN INTERRUPT FROM 21 STF DF1 NOP GIVE IT TIME JSB IOER,I NO INTERRUPT DMA.1 SFS DF1 WAS THE INTERRUPT FROM 21? JSB IOER,I NO CLC DF1,C CLEAR FLAG AND CONTROL 21 JSB JPTRP TRAP CELL = JMP DMA.2 DEF DMA.2 STF DF2 FORCE AN INTERRUPT FROM 22 NOP GIVE IT TIME JSB IOER,I NO INTERRUPT DMA.2 SFS DF2 WAS THE INTERRUPT FROM 22? JSB IOER,I NO CLF DF2 CLEAR FLAG 22 LDB CONF1 GET ADDRESS FOR CONAD OTB CONAD CONAD = DMP01 JSB JPTRP TRAP CELL = JMP DMA.3 DEF DMA.3 STF DF0 INTERRUPT AFTER SELF CONFIGURATION STC DF0 NOP GIVE IT TIME JSB IOER,I NO INTERRUPT * * (CONTINUED) * SKP DMA.3 SFS DF0 WAS THE INTERRUPT FROM 20? JSB IOER,I NO CLC DF0,C CLEAR FLAG AND CONTROL20 JSB RSTRP RESTORE JSB ILINT TO TRAP CELL LIA CONAD CHECK IF CONAD INCREMENTED BY 3 AND PAT15 MASK BIT 15 CPA CONF2 DID CONAD INCREMENT BY 3? RSS YES JSB IOER,I NO LIA CWRD1 GET CWRD1 CONTENTS CPA DMP01 WAS CWRD1 LOADED CORRECTLY? RSS YES JSB IOER,I NO LIA DMAAD GET DMAAD CONTENTS CPA DMP01+1 WAS DMAAD LOADED CORRECTLY? RSS YES JSB IOER,I NO LIA WRDCT GET WRDCT CONTENTS CPA DMP01+2 WAS WRDCT LOADED CORRECTLY? RSS YES JSB IOER,I NO LDA POINT,I GET CHIP S/C UNDER TEST ELA,CLE,ERA JSB JPTRP TRAP CELL = JMP DMA.4 DEF DMA.4 LIB DMAAD SET CONAD = DMAAD OTB CONAD LDA B3 ESTABLISH DIAGNOSE MODE 3 OTA GR STC DF1 START THE INPUT TRANSFER NOP GIVE IT TIME JSB IOER,I DMA DID NOT INTERRUPT IN TIME DMA.4 CLA DISABLE DIAGNOSE MODE 3 OTA GR CPB B,I DID THE TRANSFER WORK? RSS YES JSB IOER,I NO INB DID CONAD AND DMAAD INCREMENT? LIA CONAD GET CONTENTS OF CONAD CPB A DID IT INCREMENT? AND PAT15 MASK BIT 15 RSS YES JSB IOER,I NO LIA DMAAD GET CONTENTS OF DMAAD CPB A DID IT INCREMENT? RSS YES JSB IOER,I NO LDA DMP01+2 CHECK IF RESIDUE WAS WRITTEN ILLEGALLY SZA,RSS JSB IOER,I IT WAS WRITTEN. DMP01+2 WAS BOMBED. JSB RSTRP RESIDUE NOT WRITTEN. RESTORE TRAP CELL SKP * * *CHECK A FOUR WORD SELF CONFIGURATION * FORWD CLF 0 DISABLE INTERRUPTS LDA CONF2 GET NEXT CONFIGURATION ADDRESS OTA CONAD GIVE TO CONAD STC DF0 SELF-CONFIGURE SFS DF4 IS 24 SET? (DMA OPERATING) JSB IOER,I NO. FAULTY FLAG LIA CONAD GET CONAD AND PAT15 MASK BIT 15 CPA CONF3 DID IT INCREMENT? RSS YES JSB IOER,I NO LIA CWRD1 GET CONTENTS OF CWRD1 CPA DMP02 IS CONTROL WORD RIGHT? RSS YES JSB IOER,I NO LIA DMAAD GET CONTENTS OF DMAAD CPA DMP02+2 IS ADDRESS RIGHT? RSS YES JSB IOER,I NO - 4 WORD CONFIGURATION FAILED LIA WRDCT GET WORD COUNT CPA DMP02+3 IS ADDRESS RIGHT? RSS YES JSB IOER,I NO SKP * * *CHECK THAT THE RESIDUE IS WRITTEN IN THE WORD * COUNT LOCATION IF SPECIFIED * RESDU CCB SET WORD COUNT CONSTANT TO -1 STB DMP04+2 LDA CONF4 GET CONFIGURATION ADDRESS OTA CONAD OUTPUT TO CONAD CLC DF2,C COMPLETE PREVIOUS DMA NOP GIVE IT TIME CLC DF2,C RESTART DMA SELF CONFIGURATION NOP GIVE DMA TIME NOP SFC DF4 IS 24 CLEAR?(DMA OFF) JSB IOER,I NO. FAULTY FLAG LIA WRDCT GET WORD COUNT RESIDUE SZA SHOULD BE ZERO JSB IOER,I IT ISN'T LDB DMP04+2 GET THE WORD COUNT LOCATION DATA SZB SHOULD BE ZERO JSB IOER,I IT ISN'T CCB RESTORE WORD COUNT CONSTANT STB DMP04+2 SKP * * *INITIATE A TRANSFER WITH RECONFIGURATION UPON * COMPLETION SPECIFIED * RECON LDA CONF3 GET CONFIGURATION ADDRESS OTA CONAD GIVE TO CONAD CCB STORE A -1 STB DMP03+2 IN WORD COUNT CLC DF2,C CLEAR PREVIOUS DMA STC DF0 START SELF-CONFIGURATION NOP GIVE FIRST DMA TIME CLC DF2,C COMPLETE IT AND START SECOND DMA NOP GIVE SECOND DMA TIME CLC DF2,C COMPLETE IT REDON SFS DF0 WAIT FOR BOTH CONFIGURATIONS AND JMP RWAIT TRANSFERS TO COMPLETE CLC DF0,C CLEAR CONTROL AND FLAG 20 CLC DF1,C CLEAR CONTROL AND FLAG 21 LIA CONAD CHECK THAT CONAD INCREMENTED BY 7 AND PAT15 MASK BIT 15 CPA CONF4 DID IT? RSS YES JSB IOER,I NO LIA DMAAD GET DMAAD CONTENTS LDB DMP03+5 GET ADDRESS OF SECOND TRANSFER INB INCREMENT ADDRESS CPB A DID DMAAD INCREMENT CORRECTLY? RSS YES JSB IOER,I NO LIA WRDCT GET WORD COUNT REGISTER SZA DID IT ROLL OVER? JSB IOER,I NO LDB DMP03+2 RESIDUE WRITTEN BACK? SZA SHOULD BE ZERO JSB IOER,I IT ISN'T CCB RESTORE DATA REGISTER STB DMP03+2 TO PROPER WORD COUNT JMP WD500 CONTINUE TO THE NEXT TEST * RWAIT ISZ A GIVE IT TIME JMP REDON HAVE TRANSFERS COMPLETED? JSB IOER,I TRANSFERS DIDN'T COMPLETE - SEE REDON * * *NOTE: FOR RESIDUE RETURN TEST, THE USER SHOULD INSERT THE * CORRECT INSTRUCTION CODES IN PARENTHESIS, AS WELL * AS CHANGE THE DMA CONTROL WORD AT DMP03. SKP * * *SET UP DMA FOR A 500 WORD TRANSFER INTO * PROTECTED MEMORY, TURN ON MEMORY PROTECT, * AND EXECUTE. MPT SHOULD ALLOW TRANSFER. * WD500 JSB BUFCL CLEAR THE TRANSFER BUFFER LDA DMPX+1 GET CONFIG-DMA ADDRESS = 1010 OTA CONAD GIVE TO CONAD OTA DMAAD GIVE TO DMAAD LDA DMPX GET CONTROL WORD = IN OTA CWRD1 GIVE TO CWRD1 LDA DMPX+2 GET WORD COUNT = -500B OTA WRDCT GIVE TO WRDCT LDA POINT,I GET CHIP S/C UNDER TEST ELA,CLE,ERA JSB JPTRP TRAP CELL = JMP DMA.5 DEF DMA.5 LDA DMMTR MPT TRAP CELL = JMP DMMPT STA MTRAP STF 0 ENABLE INTERRUPTS LDA B3 ESTABLISH DIAGNOSE MODE 3 OTA GR LDA B1777 SET FENCE = 1777 OTA FENCE LDA MB260 SET A = -260B STC DF1 START THE TRANSFER STC MPT TURN ON MPT ISZ A INCREMENT A 240B TIMES JMP *-1 NOT DONE YET STPDM HLT 03 DMA SHOULD HAVE COMPLETED - STOP LIB WRDCT B = WORD COUNT RESIDUE JSB IOER,I DMA DID NOT STEAL CYCLES CORRECTLY DMA.5 CLC DF3,C DMA INTERRUPTED. INDICATE DMA ROLLOVER CLC DF1,C DMA TURN OFF DMA LIB DMAAD GET DMA ADDRESS REGISTER CONTENTS CPB B1510 WERE 500B TRANSFERS COMPLETED? RSS YES JSB IOER,I NO ADA B140 ADD 140 TO A SSA DID A INCREMENT AT LEAST 100B TIMES? JSB IOER,I NO - CPU NOT TAKING ENOUGH CYCLES JMP BUFCK CHECK THE TRANSFER BUFFER DMMPT CLC DF1,C CLEAR FLAG AND CONTROL 21 LIA VIOLA,C A MPT INTERRUPT OCCURRED - FROM STPDM? CPA STPAD JMP STPDM+1 YES LIB DMAAD NO - VIOLATION OCCURRED DURING DMA TRANSFER JSB IOER,I A = VIOLATION POINT, B = DMAAD * * *NOTE: THE CPU COUNT MAY BE OFF BY AS MANY AS 50 * DUE TO REFRESH. EXPERIMENT AND ADJUST MB260 * TO AN ACCEPTABLE MARGIN. * SKP * * *CHECK THE DATA TRANSFER BUFFER TO SEE IF THE * ADDRESS IS CONTAINED AS DATA AT EACH ADDRESS * BUFCK LDB DMPX+1 GET THE ORIGINAL DMA ADDRESS CPB B,I DOES THE DATA EQUAL THE ADDRESS? RSS YES JSB IOER,I NO INB INCREMENT THE ADDRESS CPB B1510 HAVE ALL THE ADDRESSES BEEN CHECKED? RSS YES - CONTINUE JMP *-6 NO - CHECK THE NEXT ADDRESS JSB RSTRP RESTORE TRAP CELL TO JSB ILINT LDA JSBIL RESTORE JSBIL IN MPT TRAP CELL STA MTRAP JSB BCLAD,I CLEAR THE TRANSFER BUFFER * * *SET UP A TRANSFER INTO HIGH MEMORY (20000 - 77777) * AFTER THE TRANSFER CHECK THAT CONAD AND DMAAD BOTH * INCREMENTED TO 77777. * HIMEM LDA DMPZ GET CONTROL WORD 1 = IN OTA CWRD1 GIVE TO CWRD1 LDA DMPZ+1 GET DMA/CONFIG ADDRESS = 20000 OTA DMAAD GIVE TO DMAAD OTA CONAD GIVE TO CONAD LDA DMPZ+2 GET WORD COUNT = -57777B OTA WRDCT GIVE TO WRDCT LDA POINT,I GET CURRENT I/O CHIP S/C ELA,CLE,ERA JSB JPTRP TRAP CELL = JMP DMA.6 DEF DMA.6 STF 0 ENABLE INTERRUPTS LDA B3 ESTABLISH DIAGNOSE MODE 3 OTA GR STC DF1 START THE TRANSFER LDA EOM GET END OF MEMORY COUNT CMA,INA 2'S COMPLEMENT STA TEMP1 STORE IN TEMPORARY REGISTER MCK LIA INMSK GET INTERRUPT MASK STA TEMP0 AND SAVE IT LDA PAT02 LOAD TEST PATTERN OTA INMSK AND STORE IN INTERRUPT MASK NOP GIVE IT TIME NOP A LITTLE MORE CLA CLEAR A LIA INMSK GET MASK PATTERN BACK ERA,CLE,ELA STRIP OFF LSB CPA PAT02 IS THE PATTERN CORRECT? RSS JSB IOER,I NO. MASK CHANGED DURING DMA TRANSFER LDA MB260 GET SECOND TEST PATTERN OTA INMSK OUTPUT TO CHIP NOP GIVE IT TIME NOP LIA INMSK GET MASK AGAIN ERA,CLE,ELA STRIP OFF LSB CPA MB260 IS IT THE SAME? RSS JSB IOER,I NO - ERROR LDA TEMP0 GET ORIGINAL MASK OTA INMSK AND RESTORE TO INTERRUPT REG. ISZ TEMP1 GIVE IT PLENTY OF TIME TO COMPLETE JMP MCK JSB IOER,I DMA SHOULD HAVE INTERRUPTED BY NOW DMA.6 CLC DF3,C TURN OFF DMA LIA CONAD GET CONAD CPA MIN1 DOES CONAD = 177777? RSS YES JSB IOER,I NO LIA DMAAD GET DMAAD IOR PAT10 SET BIT 15 CPA MIN1 DOES DMAAD = 77777? RSS JSB IOER,I NO JSB RSTRP YES - RESTORE THE TRAP CELL CLA DISABLE DIAGNOSE MODE 3 OTA GR HED DMA PARITY TEST * * *DMA PARITY TEST. CHECKS FOR DMA PARITY ERROR ON SELF-CONFIGURATION * *WHLE READING CONTROL WORDS WITH BAD PARITY. SHOULD CAUSE FLAGS 22 * *AND 23 TO BE SET AS WELL AS DMA SELF CONFIGURATION TO END. * DMAPR CLF 0 DISABLE INTERRUPTS CLC PES TURN OFF PARITY SYSTEM LDA DM5 GET WORD COUNTER (-5) STA TEMP0 AND STORE IN TEMP REG. LDB B1000 GET DESTINATION ADDRESS STB TEMP1 AND STORE IN TEMP. REG. LDA CONF2 GET ADDRESS OF CONFIGURATION WORD QUAD N30 LDB A,I GET IT STF PES REVERSE PARITY SENSE STB TEMP1,I STORE IT CLF PES REVERSE SENSE BACK TO ORIGINAL INA INCREMENT TO NEXT ADDRESS ISZ TEMP1 INCREMENT DESTIANTION REG. ISZ TEMP0 INCREMENT COUNTER TOWARD ZERO JMP N30 BACK FOR MORE STC PES TURN ON PARITY SYSTEM STF 0 TURN ON INTERRUPTS LDA POINT,I SET UP INTERRUPT RETURN ELA,CLE,ERA JSB JPTRP ROUTINE DEF DMPR1 TRAP CELL 20=JMP DMPR1 LDA B1000 GET STARTING DMA ADDRESS OTA DF0 SEND TO I/O CHIP STC DF0 SELF CONFIGURE NOP GIVE IT TIME JSB IOER,I DIDN'T INTERRUPT DMPR1 CLC DF0 TURN OFF DMA SFS DF3 WAS 23 SET (INTERRUPT)? JSB IOER,I NO SFS DF2 WAS 22 SET(PARITY ERROR)? JSB IOER,I NO LDB DMP02 GET CORRECT DATA STB A,I AND STORE IT INA INCREMENT POINTER STA TEMP0 STORE IT TEMPORARILY LIB DF0 GET POINTER FROM CHIP ELB,CLE,ERB CLEAR SIGN BIT CPA B IS IT CORRECT? RSS JSB IOER,I NO LDA POINT,I SET UP INTERRUPT ELA,CLE,ERA JSB JPTRP RETURN ADDRESS DEF DMPR2 TRAP CELL 20=JMP DMPR2 CLF DF2 RESET 22 CLF DF3 &23 LDA B1000 GET STARING ADDRESS OTA DF0 PUT IN CHIP STC DF0 TRY IT AGAIN NOP GIVE IT TIME JSB IOER,I SKP DMPR2 CLC DF0 CLEAR CONTROL SFS DF3 WAS 23 SET? JSB IOER,I SFS DF2 WAS 22 SET? JSB IOER,I LDA TEMP0 GET A BACK AGAIN LDB DMP02+1 GET SECOND WORD AND STB A,I RESTORE IT INA INCREMENT POINTER LDB DMP02+2 GET THIRD WORD STB A,I CORRECT IT INA INCREMENT POINTER STA TEMP0 STORE IT TEMPORARILY ADA MIN1 DECREMENT POINTER AGAIN LIB CONAD GET ENDING ADDRESS ELB,CLE,ERB CLEAR SIGN BIT CPA B IS IT CORRECT? RSS JSB IOER,I NO LDA POINT,I SET UP INTERRUPT ROUTINE ELA,CLE,ERA JSB JPTRP DEF DMPR3 TRAP CELL 20=JMP DMPR3 LDB B1000 GET START ADDRESS AGAIN OTB DF0 SEND IT TO CHIP CLF DF2 CLEAR 22 CLF DF3 &23 STC DF0 TURN ON AGAIN NOP GIVE IT TIME JSB IOER,I DIDN'T INTERRUPT DMPR3 CLC DF0 CLEAR CONTROL SFS DF3 WAS 23 SET? JSB IOER,I SFS DF2 WAS 22 SET? JSB IOER,I LDA TEMP0 GET A AGAIN LDB DMP02+3 RESTORE GOOD PARITY TO FOURTH LOCATION STB A,I INA INCREMENT POINTER STA TEMP0 STORE IT AGAIN LIB CONAD GET ADDRESS FROM CHIP ELB,CLE,ERB CLEAR SIGN BIT CPA B IS IT THE SAME? RSS JSB IOER,I NO SKP LDA POINT,I GET SELECT CODE ELA,CLE,ERA JSB JPTRP RESET TRAP CELL TO JMP DMPR4 DEF DMPR4 LDB B1000 GET STARTING ADDRESS OF SELF CONFIGURATION WORDS LDA B1400 GET NEW CONTROL WORD FOR INPUT TRANSFER STA B,I STORE IT IN PROPER LOCATION OTB DF0 SEND TO I/O CHIP CLF DF2 CLEAR FLAGS 22 CLC DF3,C (CLF DF3) AND 23 (BUG FIX ON I/O) STC DF0 SELF CONFIGURE NOP NOP GIVE IT TIME JSB IOER,I DIDN'T INTERRUPT DMPR4 CLC DF0 TURN OFF DMA SFS DF3 WAS 23 SET? JSB IOER,I NO SFS DF2 WAS 22 SET? JSB IOER,I NO LDA TEMP0 GET POINTER AGAIN INA INCREMENT IT LIB DF2 GET DMA ADDRESS ELB,CLE,ERB STRIP OFF SIGN BIT CPA B ARE THEY THE SAME? RSS YES SO CONTINUE JSB IOER,I NO HED I/O CHIP TESTS WITH MEMORY PROTECT * * *INSURE THAT THE I/O CHIP WILL NOT EXECUTE * ANY ILLEGAL I/O INSTRUCTIONS WITH MEMORY * PROTECT ON * MPTIO JSB CLC0,I INITIALIZE THE I/O SYSTEM CLF GR ENABLE GLOBAL REGISTER CLA A = 0 OTA FENCE FENCE = 0 STA MTRAP MPT TRAP CELL = NOP CLF GSC CLEAR DEVICE FLAG CCB B = 1'S OTB WRDCT WRDCT = 1'S OTB N2 N2 = 1'S STC MPT TURN ON MPT STF GSC TRY TO SET FLAG - SHOULD NOT EXECUTE SFC GSC DID IT SET? JSB IOER,I YES STC MPT TURN ON MPT LIA WRDCT TRY LIA - SHOULD NOT EXECUTE SZA WAS A ALTERED? JSB IOER,I YES STC MPT TURN ON MPT OTA N2 TRY OTA - SHOULD NOT EXECUTE LIA N2 WAS N2 ALTERED? SZA,RSS JSB IOER,I YES STF GSC SET DEVICE FLAG STC MPT TURN ON MPT CLF GSC TRY TO CLEAR FLAG - SHOULD NOT EXECUTE SFS GSC DID IT CLEAR? JSB IOER,I YES STC MPT TURN ON MPT SFS GSC TRY SFS - SHOULD NOT EXECUTE RSS JSB IOER,I IT SKIPPED STC MPT TURN ON MPT STF DF1 TRY STF DMA - SHOULD NOT EXECUTE SFC DF1 DID IT SET? JSB IOER,I YES STF DF1 SET FLAG 21 STC MPT TURN ON MPT CLF DF1 TRY CLF DMA - SHOULD NOT EXECUTE SFS DF1 DID IT CLEAR? JSB IOER,I YES * * (CONTINUED) * SKP STC MPT TURN ON MPT SFS DF1 TRY SFS DMA - SHOULD NOT EXECUTE RSS DID IT SKIP? JSB IOER,I YES STC MPT TURN ON MPT STC DF1 TRY STC DMA - SHOULD NOT EXECUTE NOP IF AN INTERRUPT OCCURS, CONTROL WAS SET STC MPT TURN ON MPT HLT 03 IS A HALT (BREAK) EXECUTED? CCA NO - SET A = 1'S OTA INMSK SET INMSK = 1'S CLA A = 0 STC MPT TURN ON MPT LIA INMSK TRY LIA INMSK - SHOULD NOT EXECUTE SZA WAS A ALTERED? JSB IOER,I YES STC MPT TURN ON MPT OTA INMSK TRY OTA INMSK - SHOULD NOT EXECUTE LIA INMSK WAS INMSK ALTERED? SZA,RSS JSB IOER,I YES STC MPT TURN ON MPT STF GR TRY STF GR - SHOULD NOT EXECUTE SFC GR DID IT SET? JSB IOER,I YES STF GR DISABLE GR STC MPT TURN ON MPT CLF GR TRY CLF GR - SHOULD NOT EXECUTE SFS GR DID IT CLEAR? JSB IOER,I YES CLF GR ENABLE GR LDA POINT,I GET CURRENT CHIP S/C ELA,CLE,ERA INA INC S/C STC MPT TURN ON MPT OTA GR TRY OTA GR - SHOULD NOT EXECUTE LIB GR GET CURRENT GR CPA B WAS IT ALTERED? JSB IOER,I YES CLB STC MPT TURN ON MPT LIB GR TRY LIB GR - SHOULD NOT EXECUTE SZB WAS B ALTERED? JSB IOER,I YES LDB B2 ESTABLISH DIAGNOSE MODE 2 OTB GR STC MPT TURN ON MPT CLA A = 0 LIA GR LIA GR IN DIAG MODE SHOULD NOT EXECUTE SZA WAS A ALTERED? JSB IOER,I YES OTA GR DISABLE DIAGNOSE MODE SKP * * *CONTINUE TEST REFERENCING DEVICE S/C WITH GR DISABLED * STF GR DISABLE GR LDB POINT,I GET CURRENT I/O CHIP S/C ELB,CLE,ERB LDA B26 GET ADDRESS OF TEST TO BE MODIFIED JSB MDSC,I GO MODIFY I/O S/C JSB CLC0,I INITIALIZE I/O STC MPT TURN ON MPT STF SC TRY STF SC - SHOULD NOT EXECUTE SFC SC DID IT SET? JSB IOER,I YES STF SC SET THE FLAG STC MPT TURN ON MPT CLF SC TRY CLF SC - SHOULD NOT EXECUTE SFS SC DID FLAG CLEAR? JSB IOER,I YES STC MPT TURN ON MPT SFS SC TRY SFS SC - SHOULD NOT EXECUTE RSS DID IT SKIP? JSB IOER,I YES STC MPT TURN ON MPT STC SC TRY STC SC - SHOULD NOT EXECUTE NOP IF AN INTERRUPT OCCURS, CONTROL WAS SET CLC SC CLEAR CONTROL LDA POINT,I GET CURRENT CHIP S/C ELA,CLE,ERA OTA GR,C GIVE TO GR AND ENABLE LDA B2 ESTABLISH DIAGNOSE MODE 2 OTA GR CLB B = 0 STC MPT TURN ON MPT MIB SC MIB SC IN DIAG MODE SHOULD NOT EXECUTE SZB WAS B ALTERED? JSB IOER,I YES OTB GR DISABLE DIAGNOSE MODE LDA JSBIL RESTORE JSB ILINT TO MPT TRAP CELL STA MTRAP JSB CLC0,I CLEAR THE I/O SYSTEM * JMP DMAT1 GO TEST THE NEXT CHIP'S DMA SKP * * *SUBROUTINE TO CLEAR THE TRANSFER BUFFER * BUFCL NOP RESERVED FOR RETURN ADDRESS LDA B1000 SET A TO THE BEGINNING OF BUFFER CLB CLEAR B STB A,I CLEAR THE BUFFER CONTENTS INA INCREMENT THE ADDRESS CPA B2000 IS THE BUFFER CLEAR? JMP BUFCL,I RETURN TO PROGRAM JMP *-4 NO - CLEAR THE NEXT LOCATION HED MULTIPLE I/O CHIP INTERRUPTS * * *EACH CHIP INTERRUPTS CORRECTLY; NOW TURN * ON ALL CHIPS AND CHECK THE HANDLING OF * MULTIPLE INTERRUPTS * * *SET FLAG AND CONTROL ON ALL CHIPS WITH * INTERRUPT SYSTEM TURNED OFF * ALLIN LDA SCTAD SET POINTER TO BEGINNING-1 STA POINT ALL.1 ISZ POINT MOVE TO NEXT TABLE ENTRY LDA POINT,I GET NEXT CHIP S/C ELA,CLE,ERA SZA,RSS IS THIS THE END OF THE TABLE? JMP ALLGO YES - BEGIN THE TEST OTA GR,C NO - LOAD GR WITH S/C AND ENABLE STF DF2 FORCE AN INTERRUPT FROM CHIP JMP ALL.1 GO SET UP THE NEXT CHIP * * *TURN ON THE INTERRUPT SYSTEM AND VERIFY * THAT EACH CHIP INTERRUPTS IN PRIORITY * ALLGO SFC TBG WAS THE LAST ROUTINE USED BY THE JMP ATBAD,I TBG INTERRUPT TEST? RETURN LDA B14 GET STATUS = MULTIPLE INTERRUPT TEST LDA SCTAD SET POINTER TO BEGINNING-1 STA POINT ALL.2 ISZ POINT MOVE TO NEXT TABLE ENTRY LDA POINT,I GET THE NEXT CHIP S/C ELA,CLE,ERA SZA,RSS IS THIS THE END OF THE TABLE? JMP TBPRI YES - GO TEST TBG INT PRIORITY OTA GR,C NO - LOAD GR WITH S/C AND ENABLE JSB JPTRP TRAP CELL = JMP INT.9 DEF INT.9 STF 0 ENABLE INTERRUPTS NOP GIVE IT TIME JSB IOER,I NO INTERRUPT INT.9 CLF 0 TURN OFF INTERRUPTS LIB CIR GET INTERRUPTING S/C LDA POINT,I WAS INTERRUPTING S/C HIGH PRIORITY? ELA,CLE,ERA CPA B RSS YES JSB IOER,I NO JSB RSTRP RESTORE JSB ILINT TO TRAP CELL CLF DF2 CLEAR CHIP FLAG JMP ALL.2 GO ALLOW NEXT INTERRUPT SKP * * *CHECK THAT TBG HAS HIGHER INTERRUPT PRIORITY * THAN ANY DEVICE INTERFACES * TBPRI CLA CLEAR THE INTERRUPT MASK OTA INMSK CLF 0 DISABLE INTERRUPTS STC TBG TURN ON TBG SFS TBG WAIT FOR TBG TO TICK JMP *-1 JMP ALLAD,I SET INTERFACE FLAGS AND CONTROLS ALLTB LDA B6 A = TRAP CELL ADDRESS JSB JPTRP TRP06 = JMP INTAT DEF INTAT STF 0 ENABLE INTERRUPTS NOP GIVE IT TIME JSB CLC0,I TURN EVERYBODY OFF JSB IOER,I NO INTERRUPTS OCCURRED INTAT JSB CLC0,I INTERRUPT GOOD - TURN EVERYBODY OFF CLC TBG,C CLEAR TBG FLAG AND CONTROL JSB RSTRP RESTORE JSB ILINT TO TRAP CELL * * *TBG WORKS CORRECTLY HED MULTIPLE I/O CHIP DMA TRANSFERS * * *ALL CHIPS HANDLE DMA CORRECTLY. NOW CHECK MULTIPLE * SIMULTANEOUS DMA TRANSFERS BY STARTING TRANSFERS ON * ALL CHIPS AND ASSURING THAT THEY DECODE THEIR PRIORITIES * CORRECTLY AND COMPLETE ALL TRANSFERS IN AN ORDERLY MANNER. * MULTI LDA SCTAD FIND OUT IF MORE THAN ONE I/O CHIP ADA B2 IS IN THE SYSTEM LDB A,I LOOK AT THE 2ND S/C TABLE ENTRY SZB,RSS IF ZERO ONLY ONE CHIP EXISTS JMP TST09 ONLY ONE CHIP - SKIP MULTI DMA LDA B15 GET STATUS = MULTIPLE DMA TEST LDB CONMD SET TEMP6 = ADDRESS OF DMD00 STB TEMP6 LDA SCTAD SET TABLE POINTER TO BEGINNING-1 STA POINT MUL.1 ISZ POINT INCREMENT THE S/C TABLE POINTER LDA POINT,I GET THE NEXT CHIP S/C SZA,RSS IS THIS THE END OF THE TABLE? JMP MUL.2 YES - MOVE TO THE TEST OTA GR,C NO - LOAD THE GLOBAL REGISTER LDA B7 ESTABLISH DIAGNOSE MODE 7 OTA GR LDB MDMCW GET CONTROL WORD 1 OTB CWRD1 GIVE TO CWRD1 LDB MDMWD GET WORD COUNT = 10B OTB WRDCT GIVE TO WRDCT LDB TEMP6,I GET DMA ADDRESS OTB DMAAD GIVE IT TO DMAAD OTB CONAD AND CONAD ISZ TEMP6 SET TEMP6 FOR THE NEXT CHIP'S DMAAD STC DF1 TURN ON DMA BUT WAIT FOR DIAG MODE 3 JMP MUL.1 CONFIGURE THE NEXT CHIP MUL.2 LDB SCTAD SET TABLE POINTER TO BEGINNING-1 STB POINT STORE IT ISZ POINT LDB POINT,I GET HIGHEST PRIORITY S/C ELB,CLE,ERB BRS,BRS SHIFT RIGHT TWICE CMB,INB COMPLEMENT, INCREMENT CLA,INA LSB IN A SET TO 1 RAL MOVE IT OVER ONE INB,SZB INCREMENT AND SKIP ON ZERO JMP *-2 DO AGAIN IF NOT ZERO IOR B11 OR IN LOWER TWO BITS CMA COMPLEMENT TO CREATE THE PROPER MASK STA TEMP9 STORE COMPLETED PATTERN OTA INMSK GIVE TO INT. REG. * * (CONTINUED) SKP LIB DMAAD GET DMAAD FROM LOW PRIORITY CHIP STB TEMP0 TEMP0 = LOW PRIORITY DMAAD STF GR DISABLE THE GLOBAL REGISTER STF 0 ENABLE INTERRUPTS LDB SCTAD GET HIGHEST PRIORITY SELECT CODE INB LDA B,I ELA,CLE,ERA JSB JPTRP HI PRIORITY TRAP CELL = JMP MDINT DEF MDINT CLB CLEAR B LDA B3 ESTABLISH DIAGNOSE MODE 3 OTA GR NOP GIVE IT TIME NOP JSB IOER,I DMA SHOULD HAVE INTERRUPTED MDINT CLF 0 TURN OFF INTERRUPTS NOP WAIT FOR FINAL DMA LIA INMSK GET INTERRUPT MASK AGAIN ERA,CLE,ELA STRIP OFF LSB CPA TEMP9 IS IT THE SAME? RSS JSB IOER,I NO - ERROR CLA CLEAR A OTA INMSK AND STORE IN INT. REG. LDB B1000 B EQUALS THE FIRST TRANSFER ADDRESS RSS SKIP FIRST TIME IN MUL.3 INB INCREMENT THE ADDRESS CPB B,I COMPARE THE DATA TO THE ADDRESS JMP MUL.3 THEY ARE EQUAL, CHECK THE NEXT ADDRESS ADB MIN1 NOT EQUAL, CHECK FOR COMPLETION MUL.4 LDA TEMP0 GET DMAAD OF LOW PRIORITY CHIP ADA B7 INCREMENT ADDRESS BY 7B CPB A,I WERE ALL THE TRANSFERS COMPLETED? RSS YES JMP MUL.E NO MUL.5 STF GR DISABLE THE GLOBAL REGISTER JSB BCLAD,I CLEAR THE TRANSFER BUFFER CLC 0,C CLEAR THE I/O SYSTEM JMP TST09 ALL TRANSFERS COMPLETED CORRECTLY SKP * * *MULTIPLE DMA ERROR ROUTINE TO SEE WHICH CHIP FAILED * MUL.E INB INCREMENT B RRL 13 STORE IN A LESS LOWER 3 BITS CLB CLEAR B AND B77 STRIP OFF REST OF WORD LEAVING COUNT SZA,RSS IS IT ZERO? JSB IOER,I YES POINTER CORRECT AS IS CMA,INA TWO'S COMPLEMENT THE COUNT ISZ POINT INCREMENT S/C TABLE POINTER INA,SZA INCREMENT COUNT AND CHECK IF ZERO JMP *-2 NOT ZERO. DO IT AGAIN JSB IOER,I POINTER CORRECT. GO DISPLAY IT SPC 2 * CLEAR I O AND WAIT FOR INTELLEGENT CARDS TO SET FLAG * CLC0R NOP CLC 0,C LDA B7 SET DIAG. MODE 7 TO DISABLE SRQ OTA GR GR IS DISABLED LEAVE IT CLA REMOVE FLAG OTA GR JMP CLC0R,I RETURN HED THE END PGEND EQU 17770B-* * * *THE I/O DIAGNOSTIC HAS SUCCESSFULLY COMPLETED! * ORG 17770B TST09 CCA CLEAR A OTA 1 SEND TO STATUS CLC 2 ENABLE ROM JSB 1 JUMP TO START OF ROM LDA 4 SET RESTART STA .END,I CLB HLT 77B ALL DONE!!!!!!! * * END